Senior Staff Verification Engineer - High-Speed Interconnect

Job Title

Senior Staff Verification Engineer - High-Speed Interconnect

Role Summary

Lead end-to-end functional verification for high-speed interconnect IP (UCIe, PCIe, DDR), from test planning through coverage closure and sign-off. Work closely with design, architecture, and silicon validation teams to ensure IP meets protocol and silicon requirements.

Provide technical leadership and mentoring to verification engineers, build maintainable UVM environments, and ensure verification catches silicon-impacting issues before tapeout.

Experience Level

Senior - 7+ years of hands-on ASIC/SoC design verification experience, with at least 3 years focused on protocol-heavy IP.

Responsibilities

Primary responsibilities include verification planning, environment development, debugging, and cross-team collaboration.

• Own verification of UCIe, PCIe, or DDR IP blocks from planning and environment bring-up through coverage closure and sign-off.
• Design, build, and extend UVM testbenches in SystemVerilog: agents, sequencers, scoreboards, coverage models, and protocol checkers.
• Develop directed and constrained-random tests targeting protocol compliance, corner cases, and multi-layer interactions.
• Debug complex RTL and testbench failures using Verdi or equivalent tools; perform waveform, protocol trace, and transaction-level analysis.
• Translate protocol specifications into executable test plans, SVA assertions, and functional coverage that map to silicon risk.
• Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and bring-up readiness.
• Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding; contribute to design and verification reviews.

Requirements

Must-have technical skills and experience for successful performance in this role; a short list of desirable additions follows.

• Must-have: 7+ years of ASIC/SoC verification experience, including a minimum of 3 years on protocol-heavy IP.
• Must-have: Deep working knowledge of at least one high-speed protocol (PCIe, UCIe, or DDR) and ability to read protocol specs and derive tests.
• Must-have: Strong UVM methodology experience: building agents, constrained-random sequences, scoreboards, and closing functional coverage.
• Must-have: Solid SystemVerilog skills, including OOP, constrained-random stimulus, and SystemVerilog Assertions (SVA).
• Must-have: Proven ability to debug complex failures with Synopsys Verdi or equivalent tools (FSDB, protocol analyzers, transaction-level debug).
• Must-have: Experience with industry simulators (VCS, Xcelium, or Questa) and familiarity with regression and coverage tools such as URG.
• Nice-to-have: Working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) is a strong plus.

Education Requirements

B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or a related discipline.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.