Senior/Staff Verification Engineer, ASIC Digital Design (DDR/LPDDR)

Job Title

Senior/Staff Verification Engineer, ASIC Digital Design (DDR/LPDDR)

Role Summary

Lead verification for DesignWare IP with primary focus on memory controllers and serial interfaces (DDR/LPDDR). Drive SystemVerilog/UVM testbench architecture, verification planning, and signoff across IP projects.

Work within the DesignWare IP Verification R&D team, collaborating with RTL designers, architects, and infrastructure engineers to ensure production-quality silicon behavior.

Experience Level

Senior - typically requires 6+ years of hands-on functional verification experience, including leadership of verification efforts.

Responsibilities

Core responsibilities include defining verification scope, building scalable verification environments, and driving metric-based closure and signoff.

• Lead and mentor a team of verification engineers through test-plan definition, regression runs, coverage closure, and signoff.
• Design and evolve SystemVerilog/UVM verification environments and reusable testbench components for synthesizable IP.
• Define and prioritize tests covering protocol compliance, corner cases, and system interactions.
• Implement and debug complex testbenches, checkers, and assertions for serial interfaces and memory controllers.
• Collect, analyze, and drive functional and code coverage to closure; identify gaps and adjust verification strategy in real time.
• Collaborate with RTL designers, architects, and circuit teams to align verification with design intent and catch issues early.
• Manage regression infrastructure and coordinate with infra teams to keep verification cycles efficient and reliable.
• Promote verification best practices and reusable verification architecture across teams.

Requirements

Must-have technical skills and leadership capabilities for the role.

• Proven track record leading verification teams through IP delivery, including planning, execution, and signoff.
• Strong experience developing and evolving SystemVerilog/UVM testbenches from scratch.
• Deep expertise in writing checkers and assertions that detect real bugs; experience with protocol-compliant checkers.
• Fluent in extracting and interpreting functional and code coverage and using metrics to drive closure.
• Experience verifying serial interface protocols and memory controllers; practical knowledge of DDR or LPDDR protocols is a strong plus.
• Ability to own end-to-end verification deliverables and participate in formal review signoff.
• Experience working across time zones and coordinating with global teams.
• Nice-to-have: familiarity with AI-assisted verification tools and regression/infra automation tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering. The role expects substantial practical verification experience (the posting indicates ~6+ years of hands-on verification work).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.