Senior Staff Validation & Verification Engineer (NVM/OTP)

Job Title

Senior Staff Validation & Verification Engineer (NVM/OTP)

Role Summary

Lead silicon validation for non-volatile memory (NVM/OTP) IP and associated analog, power, programming controller, access port/wrapper, and BIST blocks. Drive test plans, programming algorithm development, data analysis, and failure analysis across Design Validation, Characterization, and Qualification phases.

Base salary range $146,000–$219,000 (U.S.).

Experience Level

Senior-level — requires 8+ years of semiconductor product/test engineering experience.

Responsibilities

Key responsibilities include:

• Lead silicon validation through Design Validation, Characterization, and Qualification phases for NVM/OTP IP.
• Define test coverage strategies and perform DC/AC characterization with appropriate guard-banding.
• Investigate and resolve functional and reliability issues; lead root-cause failure analysis projects.
• Develop automation scripts, perform statistical analysis and data visualization, and produce test reports.
• Develop programming algorithms and test methodologies for ATE hardware and memory pattern generation.
• Collaborate with external test/reliability labs to complete qualification testing (e.g., HTOL/HTSL).
• Improve test efficiency, DOE methodology, and reduce cost through automation and process improvements.
• Mentor junior engineers and communicate technical results to cross-functional teams and management.

Requirements

Must-have skills and experience:

• 8+ years of hands-on semiconductor product/test engineering experience with strong NVM background.
• Experience with data-analysis tools such as Spotfire, Minitab, or JMP.
• Knowledge of memory fault models and advanced test methodologies for defect detection and reliability analysis.
• Familiarity with semiconductor test lab equipment: memory ATE testers (Credence Kalos 2 preferred), automated handlers, oscilloscopes, waveform analyzers, and micro-probing stations.
• Proficiency in scripting (Python or Perl) and experience with memory pattern algorithm development for ATE MTO/ALPG hardware.
• Strong analytical, problem-solving, communication, and documentation skills; experience writing silicon test reports.
• Proven ability to lead failure analysis and optimize test efficiency.

Education Requirements

BS or MS in Electrical Engineering (preferred), Engineering Physics, Computer Science, or a related technical field. The posting indicates preference for MS; equivalent practical experience may be considered.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.