Senior Staff Timing Design Engineer

Job Title

Senior Staff Timing Design Engineer

Role Summary

Lead timing (STA) and/or test (DFT) design for MCU/MPU products in the Embedded Processing Product Group. Work as part of a global backend team (Japan, China, Germany, Vietnam, India) to improve product quality, performance, and cost using EDA and AI-assisted flows.

Experience Level

Senior-level. The posting does not specify an exact years-of-experience requirement.

Responsibilities

Perform technical leadership and hands-on work in timing or test design for consumer, industrial and IoT MCUs/MPUs.

• Execute static timing analysis (STA) and timing closure using Tempus or PrimeTime.
• Perform test design and DFT implementation using Tessent or Modus.
• Drive backend design activities to meet quality, performance, and cost targets.
• Collaborate with cross-functional and international teams (backend, verification, tapeout, product groups).
• Introduce and apply EDA/AI-assisted methods and tool flows to improve efficiency.
• Mentor and guide less-experienced engineers on timing and test design practices.

Requirements

Required technical skills and experience for the role.

• Must-have: Knowledge or practical experience in either timing (STA) design or test (DFT) design.
• Nice-to-have: Experience using LSI timing/test EDA tools such as Cadence, Synopsys, Siemens.
• Nice-to-have: Hands-on experience with Tempus/PrimeTime (timing) and Tessent/Modus (DFT).

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.