Senior/Staff Static Timing Analysis (STA) Engineer

Job Title

Senior/Staff Static Timing Analysis (STA) Engineer

Role Summary

Own block-level STA signoff and contribute to full-chip timing closure for advanced-node silicon. Collaborate with physical design, synthesis, and verification teams to resolve timing and power issues and to improve STA methodologies and automation.

Experience Level

Senior - typically requires 8+ years of hands-on experience in STA and timing/power closure for advanced process nodes.

Responsibilities

Deliver STA signoff, debug timing issues, and automate flows. Key responsibilities include:

• Own and execute block-level STA signoff and support full-chip timing closure.
• Debug setup/hold, recovery/removal, clock gating, and CDC-related timing; drive resolutions with design and PD teams.
• Develop, validate, and maintain SDC constraints, clocks, exceptions, and mode/corner coverage.
• Run and analyze power signoff/support flows and correlate timing/power impacts of ECOs.
• Support timing and power ECO generation and validate fixes through signoff checks and regressions.
• Collaborate with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects.
• Use Synopsys tools (PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker) as applicable to meet PPA targets.
• Build and maintain automation (TCL/Python/Perl) for STA productivity, reporting, and regressions.
• Contribute to STA methodologies, checklists, and mentor junior engineers as needed.

Requirements

Must-have and preferred skills:

• Must-have: 8+ years of relevant STA/timing-closure experience with block ownership; full-chip exposure preferred.
• Must-have: Strong hands-on PrimeTime experience and SDC constraints development/validation.
• Must-have: Expertise in STA signoff across modes/corners (including MMMC concepts) and timing closure debugging/ECO validation.
• Must-have: Proficient scripting in TCL; ability to automate flows and reporting.
• Preferred: Experience with PrimePower/PT-PX or other power signoff tools, and familiarity with Fusion Compiler/ICC2 or DC.
• Preferred: Knowledge of parasitic extraction (e.g., StarRC), signoff correlation, and UPF/low-power considerations.
• Preferred: Scripting in Python/Perl and experience improving STA methodologies and automation.
• Strong analytical debugging, clear communication, and ability to work independently across global teams.

Education Requirements

Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.