Senior Staff/Staff Engineer, RTL Design

Job Title

Senior Staff/Staff Engineer, RTL Design

Role Summary

Lead RTL design and delivery for multi-subsystem SoCs, owning end-to-end RTL implementation, PPA optimization, and physical-design-friendly partitioning. Work closely with system architects, micro-architects and cross-functional teams to ensure on-time, first-time-right silicon.

Provide technical leadership across multiple projects, mentor junior engineers, and drive adoption of improved design methodologies and debug/security architectures.

Experience Level

Senior — requires 10+ years of hardware engineering experience.

Responsibilities

Primary responsibilities include:

• Collaborate with system and micro-architects to define implementable SoC specifications.
• Own end-to-end SoC RTL delivery, analyze and optimize designs for power, performance, and area (PPA).
• Lead RTL design and integration of multi-subsystem SoCs with multi-core, multi-power, and multi-reset domains.
• Define and drive front-end flows and checks (Lint, CDC, low-power/UPF, synthesis, DFT, STA).
• Design and integrate safety, security, and debug architectures across complex interconnects.
• Design and integrate standard interfaces (AHB, AXI, CHI) and memory interfaces (ROM, RAM, Flash, LPDDR/DDR3/4).
• Coordinate with DFT, physical design, verification, emulation, validation, lab and silicon teams to meet delivery targets.
• Support post-silicon bring-up, debug, and validation activities.
• Mentor junior engineers and track team goals; promote productivity improvements and shift-left practices.

Requirements

Must-have and preferred qualifications:

• Must-have: Strong RTL design and micro-architecture skills with proven SoC RTL delivery and PPA optimization experience.
• Must-have: Proficiency with front-end flows and checks: Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA).
• Must-have: Experience integrating standard on-chip interfaces (AHB, AXI, CHI) and common memory interfaces.
• Must-have: Demonstrated ability to work cross-functionally with DFT, physical design, verification, emulation and validation teams; strong communication skills.
• Nice-to-have: Experience with high-speed protocols such as PCIe4/PCIe6 and UCIe.
• Nice-to-have: Experience in SERDES PCS/PMA logic (scrambling/descrambling, encoding/decoding, block synchronization) and standards compliance.
• Nice-to-have: Post-silicon bring-up and debug experience.

Education Requirements

MTech or BTech in Electrical Engineering or Computer Science with 10+ years of hardware engineering experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.