Senior Staff RTL Engineer

Job Title

Senior Staff RTL Engineer

Role Summary

Senior member of the sensAI team responsible for RTL design and implementation of machine-learning compute engines on low-power FPGA platforms. The role focuses on translating ML models and operators into efficient hardware micro-architectures and optimizing datapaths for throughput, latency, and resource use.

Experience Level

Senior — 14+ years experience in RTL design (12 years required with MTech, 8 years required with PhD as specified).

Responsibilities

Key responsibilities include design, verification, and delivery of RTL for ML accelerators targeted at low-power FPGAs.

• Architect and implement RTL for machine-learning compute engines and ML operators (e.g., convolution) optimized for low-power FPGAs.
• Optimize datapaths for high throughput and low latency, and manage tradeoffs between performance, area, and power.
• Collaborate with algorithm and architecture teams to map ML models/operators into efficient hardware micro-architectures.
• Perform functional simulation and verification using industry-standard simulators.
• Work with synthesis flows, timing closure, and FPGA/ASIC implementation constraints.
• Implement image-processing and DSP algorithms in RTL and validate their hardware behavior.
• Contribute to technical documentation and cross-team communication for delivered IP blocks.

Requirements

Must-have technical skills and experience for the role; nice-to-have items are listed separately.

• Must-have: Strong RTL design experience in Verilog and SystemVerilog.
• Must-have: Practical experience with industry simulators such as Xcelium (Cadence) or VCS (Synopsys) for functional simulation.
• Must-have: Solid understanding of ML operations (for example, convolution) and neural-network accelerator concepts.
• Must-have: Experience in FPGA/ASIC synthesis flow and timing closure practices.
• Must-have: Experience implementing DSP and image-processing algorithms in RTL.
• Must-have: Working knowledge of computer architecture and memory management for hardware implementations.
• Nice-to-have: Experience or familiarity with C and SystemC.
• Nice-to-have: Background in DSP processors or neural-network accelerator microarchitecture.

Education Requirements

BE, MTech, or PhD in Electronics, Electrical, or Computer Engineering. Minimum experience in RTL design: 14 years (12 years with MTech, 8 years with PhD) as stated in the source.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.