Senior Staff RTL Design Engineer
Senior engineer responsible for RTL microarchitecture and front-end design of LPDDR PHY IP. The role focuses on producing synthesis-ready RTL, meeting timing, power, and area targets, and delivering production silicon for mobile, automotive, and AI applications.
You will work on a cross-functional team with architecture, analog, verification, and physical design engineers to resolve technical tradeoffs and improve design methodology and automation.
Senior β typically requires 10+ years of ASIC digital design experience with RTL ownership in production silicon.
Primary responsibilities include RTL design, optimization, automation, and cross-team collaboration to deliver production-quality PHY IP.
Must-have technical skills and experience, followed by preferred qualifications.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
