Senior Staff RTL Design Engineer - CPU Frontend

Job Title

Senior Staff RTL Design Engineer - CPU Frontend

Role Summary

Design and deliver CPU microarchitecture and RTL for high-performance RISC-V cores. Work within a cross-functional team including architecture, verification, performance modeling, and physical implementation to implement features, optimizations, and ISA extensions for production CPU generators.

Experience Level

Senior — 7+ years of RTL/microarchitecture design experience (specified).

Responsibilities

Primary responsibilities include designing microarchitectural features, integrating them into the generator framework, and supporting verification and physical implementation.

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve tooling for automatic configuration, documentation, verification testbenches/tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute verification plans.
• Work with physical implementation teams to meet frequency, area, and power targets.
• Collaborate with performance modeling to guide microarchitecture trade-offs and optimizations.
• Document microarchitecture and design decisions; participate in collaborative design reviews.

Requirements

Must-have technical skills, experience, and behaviors for successful candidates.

• 7+ years of CPU or RTL design experience.
• Academic or professional experience in one or more CPU areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills, including functional programming concepts, templated/metaprogramming, compiler or DSL infrastructure, intermediate representations, and test-driven development.
• Attention to detail and focus on high-quality, maintainable design.
• Ability to work effectively in cross-functional teams and share knowledge through documentation and reviews.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware.
• Knowledge of the RISC-V architecture and extensions.
• Expertise in advanced CPU subsystems (register renaming, instruction scheduling, vector units, load-store units) and verification methodologies (UVM, coverage).
• Familiarity with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.