Senior Staff RTL Design Engineer - CPU Frontend

Job Title

Senior Staff RTL Design Engineer - CPU Frontend

Role Summary

Design and deliver CPU microarchitecture and RTL for high-performance RISC-V cores, focusing on frontend features such as fetch, decode, and branch prediction. Work on configurable core generators within SiFive's Chisel/FIRRTL framework and collaborate with verification, physical implementation, and performance teams to bring hardware IP to market.

Base pay range (USD, annual): $205,740–$251,460.

Experience Level

Senior-level role. Requires 7+ years of RTL/microarchitecture design experience.

Responsibilities

Primary responsibilities include feature architecture, RTL implementation, integration, verification coordination, and cross-team collaboration.

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve tooling for automatic configuration, documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute verification test plans.
• Work with physical implementation teams to meet frequency, area, and power targets.
• Collaborate with performance modeling teams for exploration and optimization to meet performance goals.
• Produce clear microarchitecture specifications and documentation; participate in collaborative design reviews.

Requirements

Must-have skills and experience:

• 7+ years of RTL/microarchitecture design experience.
• Academic or professional experience with CPU RTL design in one or more areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware RTL languages: Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills, including functional programming concepts, templated/metaprogramming, compiler or DSL infrastructure, intermediate representations for optimization/transformation, and test-driven development.
• Attention to detail, commitment to high-quality design, and ability to work effectively in a team.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware generation.
• Knowledge of the RISC-V architecture.
• Expertise in CPU areas such as register renaming, instruction scheduling, vector units, or load-store units.
• Familiarity with verification methodologies (UVM), testbenches, and coverage-driven verification.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.