Senior Staff RTL Design Engineer - CPU Frontend

Job Title

Senior Staff RTL Design Engineer - CPU Frontend

Role Summary

Design and deliver CPU microarchitecture and RTL features for high-performance RISC-V cores. You will work on frontend CPU functions, integrate work into SiFive's Chisel/FIRRTL generator framework, and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals.

Experience Level

Senior — typically 7+ years of relevant CPU design experience.

Responsibilities

Contribute to microarchitecture, RTL implementation, integration, and verification of CPU frontend features and ISA extensions.

• Architect, design, and implement features and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automation for configuration, documentation, verification benches, and packaged software.
• Perform initial sandbox verification and work with verification engineers to develop and execute verification plans.
• Partner with physical implementation teams to meet frequency, area, and power targets.
• Collaborate with performance modeling for exploration and optimization.
• Produce clear microarchitecture specifications and documentation; participate in collaborative design reviews.

Requirements

Key technical and interpersonal qualifications. Education requirements are listed separately below.

• Must-have: 7+ years of CPU design experience with hands-on RTL experience in areas such as instruction fetch, decode, branch prediction, coherent caches, prefetching, or TLBs.
• Must-have: Proficiency in hardware RTL languages: Verilog, SystemVerilog, or VHDL.
• Must-have: Strong software engineering skills: functional and object-oriented programming, templated metaprogramming, compiler/DSL infrastructure, intermediate representations, and test-driven development.
• Must-have: Attention to detail and ability to work effectively on cross-functional teams.
• Must-have: Eligible to work in the United States; role is subject to background checks and export-control authorization where applicable.
• Nice-to-have: Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware generation.
• Nice-to-have: Familiarity with RISC-V architecture and advanced CPU topics (register renaming, scheduling, vector units, load-store unit).
• Nice-to-have: Verification experience (UVM, coverage), and familiarity with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.