Senior Staff RTL Design Engineer - CPU Frontend
SiFiveJob Title
Senior Staff RTL Design Engineer - CPU Frontend
Role Summary
Design and develop RTL and microarchitecture for high-performance RISC-V CPU cores. Work on the CPU frontend and related features while collaborating with verification, physical implementation, and performance modeling teams.
This role focuses on delivering configurable hardware IP using Chisel/FIRRTL while contributing to design tooling, verification flow, and documentation.
Experience Level
Senior — 7+ years of relevant CPU design experience.
Responsibilities
Primary responsibilities include design, integration, verification, and optimization of CPU frontend features.
- Architect, design, and implement new CPU features, performance improvements, and ISA extensions using Chisel.
- Integrate design content into the Chisel/FIRRTL framework and improve generation of documentation, verification testbenches, and tests.
- Perform initial sandbox verification and collaborate with verification teams to develop and execute verification plans.
- Work with physical implementation teams to meet frequency, area, and power targets.
- Collaborate with performance modeling for exploration and optimization.
- Develop microarchitecture specifications and maintain clear documentation for team use.
Requirements
Must-have skills and experience. Education details are summarized below under Education Requirements.
- 7+ years of CPU design experience.
- Academic or professional experience with CPU RTL design in one or more areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
- Proficiency in RTL languages: Verilog, SystemVerilog, or VHDL.
- Strong software engineering background, including functional programming, templated metaprogramming, compiler infrastructure familiarity, intermediate representations/data modeling, and test-driven development.
- Attention to detail and focus on high-quality design delivery.
- Ability to work collaboratively in multidisciplinary teams.
Nice-to-haves
- Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware.
- Knowledge of RISC-V architecture and CPU processor design topics such as register renaming, instruction scheduling, vector units, and load-store units.
- Familiarity with verification principles, UVM, coverage-driven verification, and testbench development.
- Experience with Git/GitHub, Jira, and Confluence.
Education Requirements
Bachelor's or Master's in computer science, computer engineering, electrical engineering, or a related technical field, or equivalent practical experience.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
