Senior Staff RTL Design Engineer

Job Title

Senior Staff RTL Design Engineer

Role Summary

Work on SoC microarchitecture, RTL design, and full-chip integration for high-performance Custom SoC/ASIC products. The role is part of a cross-disciplinary SoC design team focused on integrating complex IP, meeting performance/power/area targets, and delivering production-ready silicon.

Experience Level

Senior-level. Typical experience expectation: approximately 8–12 years of relevant industry experience.

Responsibilities

Contribute across the front-end SoC design flow from architecture and RTL development through integration and sign-off.

• Define microarchitecture and implement Verilog/SystemVerilog RTL for SoC-level components (interconnects, memory interfaces, global logic: reset/clocking/power management).
• Integrate complex IP and coordinate with IP teams to resolve subsystem-level issues.
• Collaborate with verification teams on test plans, functional debug, and coverage closure.
• Run design checks (lint, CDC/RDC), define timing constraints, and work with synthesis and physical design to meet PPA goals.
• Support synthesis, static timing closure, formal verification, gate-level simulation, and block-level functional verification.
• Improve design methodology and integration workflows; mentor and provide technical guidance to other engineers.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proven micro-architecture experience on complex SoC/ASIC products.
• Strong logic design and hardware debug skills.
• RTL design proficiency and hands-on experience with front-end design tools and methodologies.
• Experience with synthesis, static timing closure, formal verification, and gate-level simulation.
• Experience with high-speed, low-power, and area-optimized designs.
• Experience with multi-clock designs, DFT, resets, LEC, and lint flows.
• Proficiency in scripting (Python) for automation and design flows.
• Ability to work across architecture, verification, and physical design teams to achieve implementation requirements.
• Nice-to-have: familiarity with industry bus protocols (AXI, AHB, APB) and advanced interfaces (SerDes, HBM, PCIe, CXL) and advanced packaging integration.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field with ~8–12 years of related professional experience; or a Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with ~5–10 years of experience. Fields specified: Computer Science, Electrical Engineering, or related technical fields.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.