Principal RTL Design Engineer
Marvell TechnologyJob Title
Principal RTL Design Engineer
Role Summary
Lead micro-architecture and RTL development and HW/SW co-design for complex SoC blocks and subsystems within Marvell's Custom Solutions team. Work across architecture, verification, firmware, synthesis/STA and physical design teams to deliver production silicon.
Work focuses on high-performance data infrastructure designs integrating advanced interfaces and packaging technologies.
Experience Level
Senior — minimum 12+ years of experience in digital IC or SoC RTL design.
Responsibilities
Primary responsibilities include hands-on RTL design, integration, and leadership of design activities.
- Own RTL design, implementation, and integration of complex blocks or subsystems.
- Define and influence block- and subsystem-level micro-architecture.
- Develop high-quality, synthesizable RTL using Verilog/SystemVerilog.
- Ensure correctness through lint, CDC, RDC, and peer reviews; lead tape-out readiness reviews.
- Collaborate with verification, validation, firmware, synthesis/STA, and physical design teams to resolve integration issues.
- Identify and resolve complex functional, timing, power, and integration problems.
- Mentor and guide junior engineers and lead technical reviews.
Requirements
Must-have technical skills and experience for immediate contribution; listed below are core requirements and valuable additional experience.
- 12+ years experience in digital IC/SoC RTL design.
- Deep expertise in SystemVerilog RTL and micro-architecture.
- Strong understanding of clocking, reset, power-aware design, SoC architecture, processor cores, memory and peripheral interfaces.
- Hands-on experience with lint, CDC, RDC and a proven record of delivering blocks/subsystems on production silicon.
- Experience with synthesis, STA and physical design flows; familiarity with low-power design techniques.
- Strong debugging, problem-solving and multitasking skills; experience mentoring engineers.
- Proficient in scripting (Perl/Python) for design automation and debug.
- Nice-to-have: experience with high-speed SerDes, HBM, PCIe Gen6/7, and CXL 3.0.
- Nice-to-have: exposure to advanced process nodes (3nm/2nm) and advanced packaging (2.5D/3D, co-packaged optics).
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field as stated in the posting.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
