Senior Staff RTL Design Engineer

Job Title

Senior Staff RTL Design Engineer

Role Summary

Senior technical individual contributor on the IPG Group at the Bengaluru Design Center. Own RTL design, micro-architecture, and timing closure for high-speed Ethernet and other interconnect IP cores used in customer SoCs.

Work across global sites with verification, integration, and product teams to deliver production-quality IP that meets performance, power, and safety targets.

Experience Level

Senior-level. Typically requires substantial hands-on ASIC/IP design experience (generally 6–8+ years of relevant industry experience).

Responsibilities

Primary responsibilities include designing RTL and driving implementation and verification activities for high-speed protocol IP.

• Design and implement RTL for high-speed Ethernet and interconnect IP (100G–1.6T) focusing on low latency and timing closure.
• Translate protocol specifications into micro-architecture and detailed design documents for DesignWare IP (Ethernet, AMBA AXI/CHI, PCIe, USB, MIPI, memory controllers).
• Develop and refine directed Verilog/SystemVerilog testbenches to improve functional and code coverage and analyze coverage metrics.
• Perform technical reviews of specifications, micro-architecture docs, and RTL across global teams.
• Drive timing analysis and closure using synthesis, static timing analysis (STA), lint, CDC, and formal verification tools.
• Apply low-power design techniques and address automotive safety requirements where applicable.
• Collaborate with verification, integration, and product teams across multiple time zones to deliver IP on schedule.

Requirements

Must-have technical skills and experience for the role. Education details are listed separately under Education Requirements.

• Must-have: Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
• Must-have: Strong working knowledge of at least one protocol: AMBA (AHB/AXI/CHI), SD/eMMC, DDR, PCIe, USB, MIPI; experience with high-speed Ethernet (100G+) is a strong plus.
• Must-have: Proven ability to create micro-architecture and detailed design documents for control-path and datapath blocks (async FIFOs, DMA engines, SRAM/DPRAM interfaces).
• Must-have: Hands-on Verilog/SystemVerilog, simulation tools, synthesis flows, STA, lint, CDC, and formal verification tools.
• Must-have: Solid understanding of high-speed, low-latency design techniques and timing-closure challenges.
• Must-have: Familiarity with version control (Perforce or similar) and scripting (Perl or shell) for automation.
• Nice-to-have: Experience with datapath arithmetic algorithms (e.g., FEC), advanced timing optimizations, and automotive-grade IP development.

Education Requirements

Bachelor's degree in Electrical Engineering with 8+ years of hands-on ASIC/IP design experience, or a Master's degree with 6+ years of relevant experience. (Degrees specified in the source.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.