Senior Staff R&D Engineer, Analog Design

Job Title

Senior Staff R&D Engineer, Analog Design

Role Summary

Responsible for developing, debugging, and maintaining analog design flows (extraction, simulation, EMIR) and supporting project-specific environments for foundation IP R&D. The role works across automation, physical verification debugging, and direct collaboration with design teams to resolve complex back-end analog flow issues.

Part of the Silicon Design & Verification business working on design enablement to improve tape-out predictability and reduce cycle time.

Experience Level

Senior-level. The posting requests 6+ years of hands-on experience in VLSI design, EDA tool development, or design flow engineering.

Responsibilities

Primary responsibilities include maintaining and improving analog design flows and delivering automation and debugging support for IP projects.

• Develop, debug, and maintain analog design flows for extraction, simulation, and EMIR analysis.
• Diagnose complex issues spanning DRC/LVS, extraction, simulation, and reliability analysis; remove bottlenecks for design teams.
• Build and maintain automation using Python, TCL, and shell to eliminate manual steps and accelerate cycles.
• Configure and support project environments, including Perforce data management and LSF job scheduling.
• Collaborate directly with global design teams to deliver solutions that integrate smoothly into existing flows.

Requirements

Must-have technical skills and experience; plus items listed where indicated.

• Must-have: 6+ years in VLSI design, EDA tool development, or design flow engineering.
• Must-have: Deep knowledge of integrated analog circuit design fundamentals and the VLSI development lifecycle.
• Must-have: Proficiency in Python and scripting for automation; comfortable with TCL and shell.
• Must-have: Strong Linux/Unix command-line skills.
• Strong plus: Experience with physical verification (DRC/LVS), extraction, simulation, or reliability analysis.
• Nice-to-have: Experience with Cadence Virtuoso, UltraSim, and Synopsys tools such as ICV, StarRC, CustomCompiler, CustomSim, or Hspice.
• Nice-to-have: Experience supporting Perforce-based project data management and LSF job scheduling.
• Proven ability to debug across flow boundaries and deliver automation that other engineers can adopt and maintain.

Education Requirements

MSEE or BSEE with emphasis on VLSI, Microelectronics, or Electronics Engineering (explicitly listed in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.