Senior Staff R&D Engineer

Job Title

Senior Staff R&D Engineer

Role Summary

Senior engineer on the HAPS Production Test Team responsible for developing, validating, and shipping FPGA-based prototype solutions that enable customer ASIC designs to run before silicon. Work spans FPGA RTL implementation, synthesis/place-and-route, hardware bring-up, and validation of multi-FPGA systems.

Experience Level

Senior — typically 10+ years of relevant FPGA/RTL and hardware bring-up experience.

Responsibilities

Key responsibilities include design, implementation, and validation of production-ready FPGA prototypes and associated tooling.

• Develop FPGA-optimized implementations addressing capacity, timing, and multi-FPGA partitioning constraints.
• Own full FPGA development cycle: RTL modification, synthesis/place-and-route, timing closure, and hardware validation on AMD/Xilinx devices (Vivado).
• Drive board and system bring-up: functional validation, performance characterization, signal integrity testing, and root-cause debug.
• Build test frameworks and automation using Python and C/C++ for validation, PRBS testing, eye analysis, jitter and margin measurements.
• Design and maintain multi-FPGA partitioning strategies, inter-FPGA protocols, clock distribution, and reset architectures.
• Debug RTL, timing, clocking, and integration issues across simulation, hardware, and lab measurements using scopes, logic analyzers, and protocol analyzers.
• Collaborate with architecture, hardware, software, manufacturing, and verification teams to deliver production-ready prototyping solutions.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: 10+ years of hands-on FPGA and RTL design experience focused on multi-FPGA prototypes and production bring-up.
• Must-have: Expert-level SystemVerilog/Verilog and strong grasp of digital design fundamentals: clocking, resets, CDC, and timing analysis.
• Must-have: Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including SLR crossing and routing optimization.
• Must-have: Strong programming skills in Python and C/C++ with experience building automation and engineering tools.
• Must-have: Proficiency using lab equipment (oscilloscopes, logic analyzers, protocol analyzers, multimeters) for hardware debug and validation.
• Nice-to-have: Experience with signal integrity characterization, PRBS testing, eye diagram analysis, jitter measurement, and link margining.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.