Senior/Staff Process Engineer (Wafer Bumping/Fan-Out)
LumilensJob Title
Senior/Staff Process Engineer (Wafer Bumping/Fan-Out)
Role Summary
Lead development and technical support for wafer bumping and Fan-Out processes for silicon photonic chip wafers, working with OSAT partners or internal advanced packaging lines. Drive process integration, reliability validation, failure analysis, and NPI process documentation to achieve stable, high-yield bumping processes.
Experience Level
Senior — expects an experienced engineer. The role requests 5+ years of hands-on wafer bumping or Fan-Out process integration or development experience.
Responsibilities
Accountable for process development, characterization, and transfer of wafer bumping and fan-out processes, plus reliability and failure analysis.
- Lead process pathfinding and integration for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop; design and execute DOEs to define process windows and margins.
- Evaluate, qualify, and select manufacturing materials (photoresists, plating chemistries, underfills, solder alloys).
- Plan and execute thermal and mechanical reliability testing (TCT, HAST, HTS) and lead reliability validation efforts.
- Own failure analysis and root-cause debugging for WLCSP-specific failure modes using SEM, CSAM, cross-sectioning and other analytical tools.
- Optimize process parameters (wafer cleaning, UBM sputtering, solder plating, reflow, bump inspection) to improve uniformity and yield.
- Establish and maintain incoming wafer QC, SPC control plans, and monitor process variation for long-term stability.
- Prepare and maintain SOPs, work instructions, failure reports, and engineering change documents; support NPI and process verification.
Requirements
Must-have technical skills and hands-on experience required for immediate contribution.
- 5+ years hands-on wafer bumping or Fan-Out process integration or development experience at OSAT or IDM advanced packaging lines.
- Practical experience with photolithography, wet etching, CVD, PVD and molding processes as applied to backend bump fabrication.
- Experience with DOE methodologies, FMEA, SPC, and structured 8D problem solving.
- Familiarity with finite element concepts for warpage, thermal dissipation, and structural/mechanical integrity; ability to apply simulation results to process decisions.
- Hands-on failure analysis skills and experience using SEM, CSAM, and physical cross-sectioning techniques.
- High proficiency with analytical tools such as JMP, Minitab, or Python for data analysis and DOE.
- Nice-to-have: exposure to interposer, 2.5D/3D, chip-on-wafer-on-substrate processes.
Education Requirements
Bachelor's or Master's degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline; equivalent practical experience also acceptable.
About the Company
Company: Lumilens
Headquarters: San Jose, CA, USA
Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.
