Job Title
Senior/Staff/Principal Package Design Engineer
Role Summary
Lead package architecture and layout for advanced semiconductor memory products, spanning early co-design with silicon teams through high-volume manufacturing (HVM). Work cross-functionally with silicon design, SI/PI, OSAT assembly partners, substrate suppliers, and manufacturing teams to define, optimize, and scale package solutions for DRAM and other memory applications.
Experience Level
Senior role. Typical background: 5+ years in semiconductor package design (or 3+ years with a relevant Master's degree). Candidates with extensive DRAM experience (7+ years) are preferred for leadership on advanced memory technologies.
Responsibilities
Primary responsibilities include architecture definition, detailed package layout, and ensuring manufacturability and electrical performance through HVM.
- Lead co-design with silicon teams, business units, customers, and package architecture groups to define new product concepts and drive architecture trade-offs.
- Optimize die floorplans, interconnect schemes, and package architectures from concept through HVM.
- Lead floorplanning, placement, high-density routing, and package layout for advanced memory packages.
- Define and optimize substrate stack-ups, wire bond and flip-chip interconnect schemes, and BEOL/RDL flows; produce wire bond diagrams, interposer drawings, and manufacturing documentation.
- Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation into design decisions and perform DFM reviews and feasibility studies.
- Drive material selection, DFMEA reviews, and assembly DOEs to ensure designs are ready for HVM.
- Collaborate with OSATs, substrate suppliers, and technology development teams to define design rules, advance routing methodologies, and support global design alignment and IP development.
- Support continuous improvement, competitive analysis, and package design roadmaps.
Requirements
Must-have technical skills and experience for immediate contribution.
- Hands-on experience with advanced package EDA tools such as Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, or Siemens/Mentor Xpedition.
- Practical experience with flip-chip and wire-bond interconnects, BEOL/RDL flows, substrate stack-ups, and high-density routing.
- Proven experience partnering with SI/PI simulation teams to drive architecture and design optimization.
- Experience collaborating with OSAT assembly partners or assembly engineering organizations to deliver designs into HVM.
- Ability to create manufacturing documentation packages, wire bond diagrams, and interposer drawings; interpret parasitic modeling and validation data.
- Experience conducting DFM reviews and driving material and process decisions based on reliability and manufacturability data.
Nice-to-have:
- Experience with advanced DRAM technologies (LPDDR, HBM, GDDR) and TSV stacking, micro-bump layout, or Chip-Package Interaction (CPI) analysis.
- Familiarity with 2.5D/3D-IC, Fan-Out WLP, and System-in-Package (SiP) approaches.
- Experience defining Assembly DOEs, leading DFMEA reviews, and process/material development for HVM.
- Proficiency with AutoCAD/Autodesk Mechanical for package and interposer drawings.
- Experience leading co-design engagements and silicon floorplan optimization; interest or experience with agentic AI workflows is a plus.
Education Requirements
Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field plus 5 years of semiconductor package design experience; OR Master's degree in those fields plus 3 years of semiconductor package design experience.
About the Company
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.

Date Posted: 2026-08-20