Senior/Staff/Principal Package Design Engineer

Job Title

Senior/Staff/Principal Package Design Engineer

Role Summary

Lead design and architecture of advanced semiconductor packages from early co-design with silicon teams through high-volume manufacturing. The role partners across electrical, mechanical, and manufacturing teams to define package architectures, optimize interconnects and floorplans, and ensure manufacturability and reliability at scale.

Experience Level

Senior-level. Typical expectation: experienced individual contributor with multi-year background in semiconductor package design and delivery to high-volume manufacturing.

Responsibilities

Primary responsibilities include defining package concepts, executing layout and documentation, and driving design-for-manufacturing and quality activities.

• Lead co-design with silicon, product, and customer teams to define new package concepts and trade-offs from concept to HVM.
• Optimize die floorplans, interconnect schemes, substrate stack-ups, and package architectures for target applications (AI/datacenter, mobile, automotive, edge).
• Lead floorplanning, high-density routing, placement, and package layout activities; produce wire bond diagrams, interposer drawings, and manufacturing documentation.
• Collaborate with SI/PI teams to incorporate simulation results into design decisions and interpret parasitic modeling and validation data.
• Drive DFM reviews, DFMEA, assembly DOE definition, and partner with OSATs and substrate suppliers to ensure HVM readiness.
• Lead material selection and process flow decisions based on reliability, simulation, and manufacturability data.
• Support global design alignment, IP development, competitive analysis, and package design roadmaps.

Requirements

Must-have technical skills and experience (degree details are summarized under Education Requirements).

• Hands-on proficiency with advanced package EDA tools (example: Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, Siemens/Mentor Xpedition).
• Experience with flip chip and wire bond interconnects, BEOL/RDL flows, substrate stack-ups, and high-density routing.
• Proven experience working with SI/PI simulation teams to optimize package architecture and design.
• Experience delivering designs through HVM in collaboration with OSATs or assembly engineering organizations.
• Ability to create manufacturing-ready documentation and interpret parasitic and reliability data.
• Practical experience leading DFMEA reviews and defining assembly DOEs for manufacturability.

Nice-to-have / preferred:

• Experience with advanced DRAM technologies (LPDDR, HBM, GDDR) and 7+ years in related roles.
• Familiarity with TSV stacking, micro-bump layout, Chip-Package Interaction (CPI), 2.5D/3D-IC, FOWLP, and SiP.
• Experience with AutoCAD/Autodesk Mechanical for package and interposer drawings.
• Experience leading co-design engagements and silicon floorplan optimization; interest or experience in integrating AI/agentic workflows into design processes.

Education Requirements

Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field with 5+ years of semiconductor package design experience, or Master's degree in those fields with 3+ years of semiconductor package design experience. The posting highlights domain-specific fields (EE, ME, Materials) and associates specific experience-year expectations with degree level.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.