Senior Staff / Principal Engineer – SoC Physical Design
QualcommJob Title
Senior Staff / Principal Engineer – SoC Physical Design
Role Summary
Lead end-to-end physical design for large-scale SoCs and complex subsystems, driving projects from architecture definition through successful tapeout. Collaborate with architecture, RTL, STA, DFT, package, CAD, technology, and product teams to meet PPA and manufacturability goals.
Experience Level
Senior - role requires extensive technical leadership. Posting indicates approximately 15+ years of industry experience.
Responsibilities
Accountable for full-chip and subsystem physical implementation, signoff, and team leadership.
- Lead end-to-end physical design implementation for large SoCs and complex subsystems.
- Define and own full-chip and subsystem strategy: floorplanning, PDN, placement, CTS, routing, timing closure, SI, and physical verification.
- Drive PPA (performance, power, area) optimization and signoff across advanced process nodes.
- Develop and improve physical design methodologies, automation flows, and best practices.
- Collaborate with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product teams to meet schedules.
- Resolve complex issues: timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.
- Provide technical leadership for tapeout planning and execution to ensure high-quality silicon delivery.
- Mentor and guide junior engineers and influence strategic technology decisions.
Requirements
Must-have technical skills and experience followed by preferred items.
- Must-have: Extensive hands-on ASIC/SoC physical design experience with multiple successful tapeouts (role expects senior-level experience).
- Deep expertise in floorplanning, power delivery networks, placement, CTS, routing, timing closure, signal integrity, IR/EM analysis, and physical verification.
- Strong understanding of signoff methodologies: static timing analysis, SI, power integrity, reliability, DRC/LVS, ERC, PERC, and ESD verification.
- Experience with industry-standard EDA and signoff tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, or equivalent.
- Proven experience delivering physical design on advanced process nodes (e.g., 5nm, 3nm or equivalent) and expertise in low-power and multi-voltage designs.
- Demonstrated ability to lead technical decisions, solve complex design challenges, and manage stakeholders effectively.
- Nice-to-have: experience with high-performance CPU/GPU/AI/ML, mobile, networking, datacenter or multimedia SoCs; methodology development and flow automation; prior leadership of Physical Design teams at semiconductor product companies.
Education Requirements
Qualification examples in the posting: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting lists degree-plus-experience combinations (Bachelor's +6 years; Master's +5 years; PhD +4 years) and indicates ~15+ years of overall industry experience. Equivalent practical experience is acceptable where noted.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
