Senior Staff / Principal Engineer – SerDes Analog/Mixed-Signal Design

Job Title

Senior Staff / Principal Engineer – SerDes Analog/Mixed-Signal Design

Role Summary

Lead design and delivery of analog/mixed-signal circuits and foundation IP for high-speed SerDes targeting AI data-center connectivity. Work on transistor-level design through silicon characterization and cross-functional integration.

Experience Level

Senior-level engineer. Requires significant industry experience in analog/mixed-signal IC design and high-speed (100G+) circuit development.

Responsibilities

The primary responsibilities focus on circuit architecture, implementation, verification, and silicon bring-up for high-speed SerDes and related IP.

• Own design and development of complex analog/mixed-signal circuits for high-speed SerDes and foundation IP.
• Translate system-level specifications into circuit architectures, design strategies, and measurable implementation targets.
• Evaluate architectural alternatives and optimize performance, power, area, noise, linearity, bandwidth, and robustness.
• Lead transistor-level design, behavioral modeling, simulation, verification, and post-layout performance closure.
• Drive technical design reviews, document trade-offs, and provide guidance to other engineers.
• Support silicon bring-up, characterization, silicon-to-simulation correlation, and root-cause analysis.

Requirements

Must-have technical skills and experience required to perform the role.

• Significant industry experience in analog/mixed-signal IC design and 100G+ high-speed circuit design.
• Demonstrated expertise in transistor-level circuit design, simulation, and performance optimization.
• Proven track record taking complex circuit blocks through implementation, verification, and design closure.
• Strong understanding of circuit-level trade-offs and ability to map circuit behavior to system-level requirements.
• Proficiency with industry-standard circuit simulators and design tools.
• Strong technical communication, problem solving, and cross-functional collaboration skills.

Education Requirements

M.S. or Ph.D. in Electrical Engineering or a related field (explicitly listed in the posting).

Preferred Qualifications

Nice-to-have skills and domain-specific experience that will accelerate impact.

• Proven experience in 100G+ high-speed SerDes or other demanding analog/mixed-signal IC development.
• Experience with advanced-node CMOS technologies and challenges in parasitics, variability, power, and signal integrity.
• Expertise in any of: Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider, phase interpolators, injection-locked oscillators, multi-phase clock generators.
• Experience with high-speed DACs/line drivers, TIAs, CTLE, PGA, Cherry-Hooper amplifiers, high-speed voltage followers.
• Experience with time-interleaved SAR ADCs, track-and-hold circuits, bandgap/PTAT/LDO design, charge pumps, or auto-zero comparators.
• Experience with post-layout analysis, silicon characterization, and silicon-to-simulation correlation.
• Track record driving complex technical tasks independently and mentoring other engineers.
• Familiarity with scripting/tools such as Python or MATLAB for modeling, automation, and optimization.

Equal Opportunity & Accessibility

Upscale is an Equal Opportunity Employer. For accommodation requests during the hiring process, contact hiring@upscaleai.com (this inbox is for accommodations only).

About the Company

Company: Upscale

Upscale builds high-performance infrastructure for AI, focusing on silicon, systems, and networking to support demanding AI workloads. Backed by significant funding, the company develops advanced SerDes and mixed-signal technologies for data centers and emphasizes engineering rigor, rapid execution, and impact.