Senior Staff/Principal Engineer, AMS Verification (Power & Analog ICs)

Job Title

Senior Staff/Principal Engineer, AMS Verification (Power & Analog ICs)

Role Summary

Lead verification of digital content embedded in power, analog, and mixed-signal IC products. This senior individual-contributor role owns verification architecture, methodology, execution, and sign-off at block and full-chip levels.

Work with analog and digital teams to create scalable verification environments from specifications, drive closure of specification gaps, and provide evidence of functional correctness before tape-out.

Experience Level

Senior - 10+ years of experience in AMS verification (per job qualifications).

Responsibilities

Primary responsibilities include planning, building, and executing verification for digital functions that interact with analog circuitry.

• Own block-level and full-chip digital verification strategy and sign-off for power, analog, and mixed-signal ICs.
• Develop verification plans from product and design specifications: feature extraction, test intent, coverage goals, assumptions, and sign-off criteria.
• Design and implement SystemVerilog/UVM testbenches, agents, scoreboards, assertions, sequences, and coverage models.
• Establish verification flows, run regressions, triage failures, debug root causes, and close verification gaps.
• Apply simulation, assertion-based techniques, formal verification, and FPGA/emulation when beneficial.
• Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.
• Support DFT verification, scan/ATPG checks, production-test vector development, and gate-level/timing-aware/post-layout verification.
• Mentor engineers, drive reusable methodology and automation, and provide concise status, coverage, risk, and sign-off assessments to leadership.

Requirements

Key technical and professional requirements. "Must-have" items are listed first; "Nice-to-have" items follow.

• Must-have: 10+ years of AMS verification with substantial hands-on experience in SystemVerilog and UVM.
• Proven ownership of block-level and full-chip verification environments and demonstrated sign-off for complex semiconductor products.
• Strong knowledge of functional verification, assertion-based techniques, regression frameworks, coverage closure, and debug methodologies.
• Experience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal ICs.
• Good understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces (SPI, I2C, UART).
• Working knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification to enable cross-flow collaboration.
• Experience with scripting or automation using Python, TCL, Perl, shell, or similar languages.
• Proven ability to mentor engineers, establish verification methodology, and lead technical reviews; self-driven and able to deliver under tight schedules.
• Nice-to-have: formal verification, FPGA/emulation-based verification, deeper STA/DFT experience, and silicon bring-up/root-cause analysis experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.