Senior Staff / Principal Engineer, AMS Verification

Job Title

Senior Staff / Principal Engineer, AMS Verification

Role Summary

Lead verification of digital content embedded in power, analog, and mixed-signal IC products as a senior individual contributor. Own verification architecture, methodology, execution, and sign-off at block and full-chip levels.

Work with architecture, analog, digital, applications, and test teams to close specification gaps, establish verification flows, and provide evidence that designs meet functional and product requirements prior to tape-out.

Experience Level

Senior - typically requires 10+ years of AMS verification experience with substantial hands-on SystemVerilog and UVM work.

Responsibilities

Key responsibilities include end-to-end verification strategy, environment development, and technical leadership for mixed-signal products.

• Own block-level and full-chip digital verification strategy for analog/mixed-signal ICs (power, PMICs, automotive, audio, etc.).
• Develop verification plans from product and design specifications including feature extraction, test intent, coverage goals, and sign-off criteria.
• Design and implement SystemVerilog/UVM testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models.
• Set up and run regressions, triage failures, debug, and drive closure to sign-off.
• Apply simulation, assertion-based verification, formal methods, FPGA/emulation where appropriate.
• Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.
• Collaborate on mixed-signal modeling, DFT, scan/ATPG checks, gate-level/timing-aware verification, and post-layout verification.
• Support silicon bring-up, device evaluation, root-cause analysis, and document workarounds for errata.
• Mentor engineers, promote reusable methodology, automation, metrics, and provide concise status/coverage/risk/sign-off reports.

Requirements

Must-have technical skills and attributes; candidates should be able to lead verification execution and methodology without formal people-management authority.

• Hands-on experience with SystemVerilog and UVM testbench development and verification environments.
• Strong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies.
• Experience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal ICs.
• Good understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces (SPI, I2C, UART).
• Working familiarity with synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification for cross-flow collaboration.
• Scripting/automation experience (Python, TCL, Perl, shell or similar).
• Proven ability to establish verification methodology, mentor engineers, and lead technical reviews.
• Ability to work autonomously, handle ambiguous specifications, and deliver under tight schedules in multisite/multicultural environments.
• Nice-to-have: FPGA/emulation experience, deep formal-methods exposure, production-test vector development experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.