Senior Staff Physical Design Engineer

Job Title

Senior Staff Physical Design Engineer (Austin Hiring Event)

Role Summary

On-site engineering role focused on physical design and methodology for next-generation, high-performance processor/ASIC chips in advanced CMOS processes. Work within a cross-functional team to drive implementation, integration, and design closure for large, complex digital designs targeted at server and networking applications.

Experience Level

Senior — typically requires 5+ years of professional experience in back-end/physical design; experience expectations vary with advanced degrees (see Education Requirements).

Responsibilities

Core responsibilities include design implementation, integration, and automation to deliver tapeout-ready silicon.

• Collaborate with Digital, RTL, and Analog teams to ensure timely design convergence and integration.
• Implement and support multi-voltage designs through place-and-route, static timing, and physical verification using industry EDA tools.
• Drive assembly and design closure with RTL/design teams across the flow from RTL to GDS.
• Develop scripts and automation (Shell, Python, TCL) to extract data and improve productivity.
• Mentor and provide technical direction to junior engineers to achieve project milestones.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5+ years experience in back-end physical design (must-have).
• Expertise in full-chip and sub-hierarchy integration and experience with large design tapeouts (must-have).
• Strong understanding of RTL-to-GDS flows and physical design methodology (must-have).
• Proficient scripting skills in Python, Tcl; familiarity with Shell and Perl is expected (must-have).
• Good knowledge of digital logic, computer architecture, and Verilog (must-have).
• Familiarity with static timing analysis tools (e.g., Tempus, PrimeTime) and EM/IR analysis tools (e.g., Voltus, PrimeRail) (nice-to-have).
• Experience with physical verification and formal tools (e.g., Calibre, LEC, Formality) (nice-to-have).
• Experience with multi-voltage and low-power design techniques (nice-to-have).
• Experience with Cadence Innovus preferred (nice-to-have).
• Ability to work on-site at the assigned team location; relocation assistance available for qualified candidates (must-have).
• May require eligibility to access export-controlled technology; candidates may be subject to export license review (must-have).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field with 5–10 years of relevant experience; or Master’s or PhD in Computer Science, Electrical Engineering, or related fields with ~3–5 years of experience. Equivalent professional experience is accepted in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.