Senior/Staff NPI Wafer Bumping & Fan-Out Process Engineer

Job Title

Senior/Staff NPI Wafer Bumping & Fan-Out Process Engineer

Role Summary

Lead process development, integration, and technical support for wafer bumping and fan-out manufacturing for silicon photonic chip wafers. Drive NPI process pathfinding, yield improvement, failure analysis, and reliability validation across cross-functional teams.

Work includes process characterization, material qualification, process control, and documentation to support production handoff and long-term stability.

Experience Level

Senior — typically requires 5+ years of hands-on wafer bumping or fan-out process development or integration experience in OSAT or IDM advanced packaging environments.

Responsibilities

Primary responsibilities include leading technical development and ensuring process robustness during NPI and scale-up.

• Lead development and technical support for wafer bumping and fan-out processes for silicon photonic wafers.
• Design and optimize early-stage process flows: thin-film sputtering, photolithography, electroplating, ball drop, and reflow; run DOE to define process windows and margins.
• Evaluate and qualify manufacturing materials (dielectric photoresists, plating chemistries, underfills, solder alloys).
• Plan and execute reliability testing and DOE for thermal and mechanical stress (TCT, HAST, HTS).
• Own failure analysis and root-cause diagnostics for WLCSP-specific failure modes using SEM, CSAM, physical cross-sectioning, and other analytics.
• Optimize bumping process steps: wafer cleaning, UBM sputtering, solder ball plating, reflow, and bump inspection to improve uniformity and yield.
• Establish and maintain SPC control plans; monitor process variation and long-term stability.
• Prepare and maintain process SOPs, work instructions, failure reports, and engineering change documentation to support NPI and process verification.

Requirements

Must-have technical skills and practical experience; nice-to-have items listed separately.

• 5+ years of hands-on wafer bumping or fan-out process integration or development experience at OSAT or IDM advanced packaging lines.
• Practical expertise in photolithography, wet etching, CVD, PVD, and molding processes adapted for backend bump fabrication.
• Experience designing and executing DOE and reliability validations; familiarity with TCT, HAST, and HTS methods.
• Strong failure-analysis skills and experience with SEM, CSAM, physical cross-sectioning, and root-cause methodologies.
• Solid command of process control and quality tools: FMEA, SPC, and structured 8D problem solving.
• Proficiency with analytical/statistical tools such as JMP, Minitab, or Python for data analysis and DOE interpretation.
• Knowledge of finite element simulation principles related to warpage, thermal dissipation, and structural integrity.
• Nice-to-have: exposure to interposer, 2.5D/3D, and chip-on-wafer/substrate advanced packaging flows.

Education Requirements

Bachelor's or Master’s degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or a related technical discipline — or equivalent practical experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.