Senior Staff Layout Design Engineer

Job Title

Senior Staff Layout Design Engineer

Role Summary

Design and deliver full-custom layouts for embedded memory IP (SRAM, register files, ROM compilers) across advanced process nodes. Own layout implementation, verification, automation, and handoff while collaborating with circuit designers, memory compiler architects, and product engineering to meet area, performance, and power targets.

Experience Level

Senior-level. This role expects multiple years of hands-on layout experience focused on embedded memories; see Education Requirements for degree-specific experience guidance.

Responsibilities

Primary responsibilities include:

• Design and own full-custom layouts for embedded memory blocks, including floor plans, cell placement, periphery blocks, and signal/power routing.
• Develop power grid architectures and perform IR drop and electromigration analysis; iterate with circuit teams to close power and timing issues.
• Execute physical verification (DRC/LVS) using tools such as Calibre or ICV, debug violations, and drive layouts to signoff-clean status.
• Back-annotate layout parasitics and perform iterative timing closure with circuit designers.
• Automate layout flows and repetitive tasks using scripting (TCL, Perl, C-shell) to improve productivity and consistency across memory variants.
• Support release cycles: documentation, design rule checks, handoff to product engineering and customers.
• Mentor junior layout engineers and contribute to methodology and best-practice development for next-generation process nodes.

Requirements

Must-have skills and technologies:

• Extensive hands-on experience with full-custom layout design for embedded memories: floorplanning, placement, power grid design, and signal routing.
• Proficiency with layout tools such as Cadence Virtuoso or Custom Compiler and physical verification tools such as Mentor Calibre or Synopsys ICV.
• Strong understanding of IR drop and electromigration analysis and experience with tools such as XARA or RedHawk to close power-integrity issues.
• Solid knowledge of physical design methodology across all phases: floor planning, place and route, DRC/LVS verification, and signoff procedures.
• Scripting capability in TCL, Perl, or C-shell to automate layout tasks and improve design flow efficiency.
• Experience collaborating with circuit designers and memory compiler architects to translate specifications into manufacturable, verified layout deliverables.

Nice-to-have:

• Experience with memory compiler development, block placement strategies, and parasitic-aware layout optimization.

Education Requirements

Diploma in Electronics Engineering with 8+ years of layout design experience; or BE/BTech with 6+ years; or MS with 4+ years in a directly relevant role working on embedded memory layout or similar physical design tasks.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.