Senior Staff IP RTL Design Engineer

Job Title

Senior Staff IP RTL Design Engineer

Role Summary

Member of Central Engineering responsible for architecting and delivering production-quality RTL for UCIe, HBM and other high-speed interface IP. The role spans micro-architecture definition through production RTL and offers both individual contributor and technical lead responsibilities.

Experience Level

Senior-level — 8–14 years of hands-on digital design experience delivering silicon-proven IPs or SoCs.

Responsibilities

Deliver and lead RTL design efforts for high-speed interface IP, ensuring quality and reusability.

• Architect, design, and implement RTL for UCIe, HBM and other high-speed interface IP.
• Own micro-architecture and RTL development for medium-to-high complexity digital blocks.
• Execute RTL coding, synthesis, CDC/RDC analysis, linting, and debugging; support test and bring-up activities.
• Collaborate with Architecture and Verification teams to define test plans and coverage strategies and achieve verification closure.
• Participate in design reviews to improve IP quality, robustness, and reusability.
• Provide technical leadership: mentor junior engineers and review designs to build a high-performance team.

Requirements

Must-have technical skills and proven delivery of production designs. (Education degree requirements are summarized below.)

• Strong domain expertise in high-speed protocols such as UCIe, HBM, Ethernet, DDR, PCIe, USB (direct UCIe/HBM experience strongly preferred).
• Extensive hands-on experience with SystemVerilog/Verilog; VHDL is a plus.
• Proven experience with RTL quality and sign-off flows including lint and CDC/RDC analysis (e.g., SpyGlass or equivalent).
• Solid understanding of synthesis, static timing analysis (STA), formal checking, and interactions with place & route.
• Good grasp of SoC architecture including processor cores, memories, interconnects, and peripheral interfaces.
• Demonstrated ability to deliver production-quality designs on aggressive schedules and strong debugging/problem-solving skills.
• Effective cross-functional collaboration and ability to influence technical direction.

Nice to have:

• Experience with low-power design techniques and advanced clocking architectures.
• Exposure to post-silicon debug and silicon bring-up.
• Prior experience delivering reusable IPs across multiple products or process nodes.

Education Requirements

BSEE or MSEE (or equivalent) in Electrical Engineering or a related field; the posting also allows equivalent practical experience. The role expects approximately 8–14 years of hands-on digital design experience delivering silicon-proven IPs or SoCs.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.