Senior Staff Interface IP Verification (Pre-Silicon: PCIe, CXL, DDR, Ethernet)

Job Title

Senior Staff Interface IP Verification (Pre-Silicon - PCIe, CXL, DDR, Ethernet)

Role Summary

Lead end-to-end verification of high-speed Interface IP (PCIe, CXL, DDR, Ethernet) from architecture review through silicon signoff. Build scalable, reusable UVM-based testbenches, define verification strategies, and drive signoff quality.

Work closely with architecture, design, firmware, and systems teams; mentor verification engineers and influence verification methodology across the Interface IP portfolio.

Experience Level

Senior - 8+ years of hands-on ASIC/SoC verification experience.

Responsibilities

Deliver and own verification activities and environment development for interface IP:

• Own end-to-end verification from architecture review to silicon signoff for PCIe, CXL, DDR, and Ethernet IP.
• Design and maintain reusable UVM-based verification environments across product lines.
• Define verification strategies and test plans addressing protocol compliance, performance corner cases, and system-level integration.
• Develop constrained-random, coverage-driven tests to achieve functional coverage closure and signoff quality.
• Debug complex issues across RTL, protocol state machines, timing, and testbench infrastructure using industry simulators.
• Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early.
• Mentor and train verification engineers on UVM methodology, coverage analysis, and debugging techniques.

Requirements

Key technical skills and experience required; degree information is summarized in Education Requirements below.

Must-have:

• Deep expertise in SystemVerilog and UVM methodology; proven track record building scalable verification environments.
• Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with ability to translate specs into verification requirements.
• Experience developing constrained-random, coverage-driven verification solutions and achieving functional signoff.
• Strong debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim.
• Experience leading verification efforts and mentoring engineers.

Nice-to-have:

• Experience with verification IP development, assertion-based verification, or formal methods.
• Familiarity with modern SoC architectures and high-speed communication interface integration.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (as stated in the source). The posting also specifies 8+ years of hands-on ASIC/SoC verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.