Senior Staff - Interface IP Verification (Pre-Silicon: PCIe/CXL/DDR/Ethernet)
SynopsysJob Title
Senior Staff - Interface IP Verification (Pre-Silicon: PCIe/CXL/DDR/Ethernet)
Role Summary
Lead end-to-end pre-silicon verification for high-speed Interface IP (PCIe, CXL, DDR, Ethernet). Work on scalable UVM-based testbenches, define verification strategies, and drive signoff-quality coverage for IP integrated into complex SoCs and systems.
Join a global verification team collaborating with architecture, design, firmware, and systems engineers to prevent protocol and integration bugs before silicon.
Experience Level
Senior-level — requires 8+ years of hands-on ASIC/SoC verification experience.
Responsibilities
Primary responsibilities include ownership of verification flow, environments, and signoff for interface IP.
- Own end-to-end verification from architecture review through silicon signoff for Interface IP (PCIe, CXL, DDR, Ethernet).
- Design and evolve reusable, scalable UVM-based verification environments across product lines.
- Define verification strategies and test plans covering protocol compliance, performance corner cases, and system-level integration.
- Develop constrained-random, coverage-driven test scenarios targeting functional coverage closure and signoff quality.
- Debug multi-layer issues across RTL, protocol state machines, timing, and testbench infrastructure using industry simulators.
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early.
- Mentor and lead verification engineers on methodology, coverage analysis, and debugging best practices.
Requirements
Must-have technical skills and practical experience; listed items denote core requirements and relevant strong preferences.
- 8+ years of hands-on ASIC or SoC verification experience (senior-level contributor/technical lead).
- Deep expertise in SystemVerilog and UVM methodology; track record building scalable verification environments.
- Strong protocol experience in at least one of PCIe, CXL, DDR, or Ethernet with ability to convert specs into verification requirements.
- Experience developing constrained-random, coverage-driven verification solutions and achieving functional signoff.
- Proven debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim.
- Experience mentoring engineers and leading technical verification discussions.
- Nice-to-have: verification IP development, assertion-based verification or formal methods, and knowledge of modern SoC architectures and high-speed interfaces.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required as listed in the posting.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
