Senior Staff Interface IP Verification Engineer (Pre-Silicon: PCIe/CXL/DDR/Ethernet)
SynopsysJob Title
Senior Staff Interface IP Verification Engineer (Pre-Silicon: PCIe/CXL/DDR/Ethernet)
Role Summary
Lead end-to-end pre-silicon verification of Interface IP (PCIe, CXL, DDR, Ethernet). Own verification strategy, build reusable UVM/SystemVerilog testbenches, and drive signoff-quality coverage for IP used in data center, AI, and high-performance systems.
Work on a global engineering team collaborating with architecture, design, firmware, and systems engineers; provide technical leadership and mentor other verification engineers.
Experience Level
Senior-level role. The posting expects 8+ years of hands-on ASIC/SoC verification experience.
Responsibilities
Primary responsibilities include defining verification strategy, building environments, debugging complex issues, and mentoring engineers.
- Own end-to-end verification of Interface IP blocks (PCIe, CXL, DDR, Ethernet) from architecture review through silicon signoff.
- Design and evolve reusable UVM/SystemVerilog verification environments scalable across product lines.
- Define verification strategies and test plans that address protocol compliance, performance corner cases, and system-level integration.
- Develop constrained-random, coverage-driven tests targeting functional coverage closure and signoff quality.
- Debug complex issues across RTL, protocol state machines, timing, and testbench infrastructure using industry simulators.
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early.
- Mentor and train verification engineers on UVM methodology, coverage analysis, and debugging techniques.
Requirements
Must-have technical skills and experience; followed by desirable skills.
- 8+ years of ASIC/SoC verification experience focused on interface or IP verification.
- Deep expertise in SystemVerilog and UVM with experience building scalable verification environments.
- Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet and ability to translate specs into verification requirements.
- Experience developing constrained-random and coverage-driven verification solutions for signoff.
- Proven debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim.
- Able to define verification strategies, write test plans, and drive coverage to signoff criteria.
Nice-to-have:
- Experience with verification IP development, assertion-based verification, or formal methods.
- Familiarity with modern SoC architectures and high-speed communication interfaces.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (as stated in the posting).
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
