Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe / CXL / DDR / Ethernet)

Job Title

Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe / CXL / DDR / Ethernet)

Role Summary

Lead end-to-end pre-silicon verification for interface IP (PCIe, CXL, DDR, Ethernet) from architecture review through silicon signoff. Work on UVM/SystemVerilog testbenches, develop verification strategies, and collaborate with architecture, design, firmware and systems teams.

The role emphasizes technical leadership, reusable verification infrastructure, and mentoring engineers to deliver signoff-quality verification for Interface IP used in data center, AI, and high-performance systems.

Experience Level

Senior-level; requires substantial experience (posting specifies 8+ years of ASIC/SoC verification experience).

Responsibilities

Primary responsibilities include designing and executing verification plans, building reusable testbenches, and driving signoff activities.

• Own end-to-end verification of interface IP blocks (PCIe, CXL, DDR, Ethernet) through silicon signoff.
• Design, build and evolve UVM-based, reusable verification environments across product lines.
• Define verification strategies and test plans covering protocol compliance, performance corner cases, and system-level integration.
• Develop constrained-random, coverage-driven test scenarios to achieve functional coverage closure and signoff readiness.
• Debug multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using industry simulators.
• Collaborate with architecture, design, firmware and systems teams to surface and resolve issues early.
• Mentor and guide verification engineers on UVM methodology, coverage analysis, and debugging best practices.

Requirements

Concise list of required technical skills and desirable additions.

• Must-have: Deep expertise in SystemVerilog and UVM methodology; proven track record building scalable verification environments.
• Must-have: Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet and ability to translate specs into verification requirements.
• Must-have: Experience developing constrained-random, coverage-driven verification solutions and achieving functional signoff.
• Must-have: Strong debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim (or equivalent).
• Must-have: Demonstrated ability to lead verification strategy and mentor junior engineers.
• Nice-to-have: Verification IP development, assertion-based verification, or formal methods experience.
• Nice-to-have: Knowledge of modern SoC architectures and high-speed communication interfaces.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is specified in the posting (experience requirement also stated as 8+ years of ASIC/SoC verification experience).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.