Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe/CXL/DDR/Ethernet)

Job Title

Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe/CXL/DDR/Ethernet)

Role Summary

Lead pre-silicon verification for high-performance interface IPs (PCIe, CXL, DDR, Ethernet) within the ASIC/Interface IP verification organization. Work with IP architects, RTL designers, and software teams to plan, implement, and close verification for complex interface protocols.

Drive verification strategy, develop robust testbenches and automation, and provide technical leadership during bring-up and pre-silicon validation.

Experience Level

Senior-level - typically 7+ years of relevant verification experience (protocol/interface IP verification, leadership of verification projects).

Responsibilities

Accountable for verification delivery, technical direction, and cross-functional coordination for interface IP projects.

• Define verification strategy, coverage goals, and test plans for PCIe, CXL, DDR, and Ethernet IPs.
• Design and implement SystemVerilog/UVM testbenches, stimulus, and verification components.
• Lead protocol compliance and corner-case validation, including stress and performance tests.
• Integrate emulation/FPGA prototypes and support pre-silicon bring-up activities.
• Analyze failures, root-cause silicon and simulation bugs, and coordinate fixes with design teams.
• Develop and maintain verification automation, CI flows, and regression frameworks.
• Mentor and review work of verification engineers; provide technical guidance and code reviews.
• Collaborate with architects, firmware, and system teams to ensure interoperability and system-level goals.

Requirements

Minimal and preferred skills for successful performance in this role.

• Must-have:
  • Proven experience verifying interface IPs such as PCIe, CXL, DDR, or Ethernet at pre-silicon level.
  • Strong SystemVerilog and UVM experience; familiarity with functional coverage and assertions.
  • Experience with emulation/FPGA-based verification, hardware bring-up, and debug methodologies.
  • Proficiency in scripting languages (Python, Perl, Tcl) for automation and data processing.
  • Ability to drive verification plans, collaborate across teams, and close coverage to project timelines.
• Nice-to-have:
  • Experience with formal verification or assertion-based verification flows.
  • Familiarity with Synopsys verification toolchain and IP verification flows.
  • Prior experience in leading verification teams or technical project leadership roles.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.