Senior Staff Interface IP Verification Engineer - Pre-Silicon (PCIe/CXL/DDR/Ethernet)
SynopsysJob Title
Senior Staff Interface IP Verification Engineer - Pre-Silicon (PCIe/CXL/DDR/Ethernet)
Role Summary
Lead pre-silicon verification for Interface IP (PCIe, CXL, DDR, Ethernet). You will define verification strategy, build scalable UVM environments, drive functional signoff, and collaborate with architecture and design teams to ensure IP quality.
This role combines hands-on verification, technical leadership, and mentorship on a global team delivering IP for data center, AI, and high-performance systems.
Experience Level
Senior - requires 8+ years of hands-on ASIC/SoC verification experience.
Responsibilities
Primary responsibilities include ownership of verification flow and delivering signoff-quality testbenches and coverage.
- Own end-to-end verification from architecture review through silicon signoff for Interface IP blocks (PCIe, CXL, DDR, Ethernet).
- Design and evolve reusable UVM-based verification environments across product lines.
- Define verification strategies and test plans covering protocol compliance, performance corner cases, and system integration.
- Develop constrained-random, coverage-driven tests and drive functional coverage closure.
- Debug multi-layer issues spanning RTL, protocol state machines, timing, and testbench infrastructure using industry simulators.
- Collaborate with architecture, design, firmware, and systems teams to find and fix issues early.
- Mentor and lead verification engineers on methodology, coverage analysis, and debugging best practices.
Requirements
Must-have technical skills and preferred qualifications.
- Must-have: Deep expertise in SystemVerilog and UVM methodology; track record building scalable verification environments.
- Must-have: Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet and ability to translate specs into verification requirements.
- Must-have: Experience developing constrained-random and coverage-driven verification solutions to achieve functional signoff.
- Must-have: Strong debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim.
- Must-have: Demonstrated ability to lead verification efforts and mentor other engineers.
- Nice-to-have: Experience with verification IP development, assertion-based verification, or formal methods.
- Nice-to-have: Knowledge of modern SoC architectures and high-speed communication interface design.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or a closely related technical field). The posting specifies 8+ years of ASIC/SoC verification experience in addition to the degree requirement.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
