Senior Staff Integration Design Engineer

Job Title

Senior Staff Integration Design Engineer

Role Summary

Lead integration of IP blocks (including DDR PHY) into sector- and full-chip FPGA platforms for the San Jose design team. Drive digital and custom implementation flows, produce sign-off collateral, and coordinate cross-functional teams to deliver tapeout-ready sector releases.

Experience Level

Senior-level; requires 15+ years of experience in ASIC, SoC, or FPGA design and product development.

Responsibilities

Primary responsibilities include sector integration, implementation flow ownership, verification, power correlation, and cross-team coordination.

• Integrate IP blocks into shared HPIO sectors and produce sector- and full-chip views, models, and collateral for sign-off.
• Create and maintain sector-level design constraints (SDC), including flat SDC generation that reconciles clock and constraint conflicts across IP sources.
• Run and maintain the digital implementation flow: RTL updates, synthesis (white-box/black-box), logical equivalence checking (LEC), static timing analysis (STA), and DFT scan integration.
• Support custom/physical design integration: custom cell reuse, parasitic (SPEF) extraction with dummy fill for STA sign-off, and clock-critical signal routing/shielding review.
• Execute full design verification regressions and sign-off checks for each sector release; manage version-controlled releases of netlists, SDC, and related collateral.
• Track and resolve sector-level design issues via the engineering issue tracker and publish release notes and status to cross-functional stakeholders.
• Integrate IP-level power data into full-chip power models and validate current/power assumptions per supply domain for board/system power budgeting.
• Correlate SPICE/PnR simulation power results with silicon bench and production test data and support production test screen definition.

Requirements

Required technical skills and experience. See Education Requirements below for degree expectations.

• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Proven expertise in custom and digital design implementation for IP/sector integration.
• Strong proficiency in Verilog and SystemVerilog.
• Experience with synthesis, static timing analysis (STA), logical equivalence checking (LEC), and DFT flow/ATPG generation.
• Working knowledge of SPICE-class circuit simulation and CMOS low-power design concepts (leakage, dynamic power, corner analysis).
• Familiarity with Cadence Virtuoso and custom schematic/layout tools and parasitic extraction workflows.
• Proficient in scripting and automation: Perl, TCL, Shell, Skill, Python.
• Familiarity with issue tracking and release workflows (e.g., JIRA) in a hardware engineering environment.
• Experience coordinating cross-functional teams and leading projects through planning, tapeout, and silicon characterization/validation.

Nice-to-have:

• Experience in FPGA/CPLD design and integration.
• Experience across multiple process nodes and foundries (e.g., TSMC, Samsung).
• IP and full-chip functional verification experience.

Education Requirements

Bachelor's or Master's degree (BS or MS) in Electronics, Electrical, Computer Engineering, or a closely related technical field.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.