Senior Staff Hardware Qualification Engineer
D MatrixJob Title
Senior Staff Hardware Qualification Engineer
Role Summary
Technical lead responsible for final qualification and reliability of next-generation AI compute platforms. Define and execute qualification strategies from ASIC and package level through rack-scale systems to ensure production-ready hardware for 24/7 data-center operation.
Work cross-functionally with Design, Thermal, Firmware teams and Contract Manufacturers to translate qualification findings into design and process improvements.
Experience Level
Senior-level — 12+ years of experience in hardware qualification or reliability engineering for high-performance computing (HPC), servers, or networking hardware.
Responsibilities
Lead, define, and execute hardware qualification programs across multiple system levels.
- Define and run EVT/DVT/PVT qualification plans for PCIe cards, OAM modules, chassis, and rack systems.
- Design and lead HALT/HASS, thermal cycling, humidity, vibration and other stress/reliability tests to find marginalities in high-power ASIC designs.
- Oversee signal and power integrity validation for high-speed SerDes (112G/224G/PCIe), LPDDR, CoWOS, and complex PDN transients.
- Drive failure analysis using X-ray, CT, SEM/EDX to determine root causes and recommend corrective actions.
- Qualify high-bandwidth interconnects and verify PCIe Gen5/6 link stability and similar interfaces.
- Coordinate cross-functional actions with Design, Thermal, and Firmware teams to implement hardware fixes based on qualification data.
- Manage relationships with contract manufacturers and JDMs to align on test methodologies and production outgoing quality limits (OQL).
Requirements
Must-have technical skills and experience required to perform the role.
- 12+ years of hands-on hardware qualification or reliability engineering experience in HPC, server, or networking equipment.
- Deep knowledge of JEDEC, IPC, and Telcordia reliability standards.
- Expert-level diagnostic experience with high-speed oscilloscopes, logic analyzers, and environmental chambers.
- Proficiency with statistical reliability methods (Weibull analysis, DOE) and tools such as JMP or Minitab.
- Experience leading failure analysis and root-cause investigations at system and package levels.
- Proven ability to work with CMs/JDMs and influence cross-functional engineering teams.
Nice-to-have:
- Experience qualifying air and liquid cooling components (CDUs, cold plates, leak detection) for high-TDP systems.
- Background in ASIC/package-level reliability (electromigration, thermal stress analysis).
- Familiarity with Python or LabVIEW for test automation.
Education Requirements
BS or MS in Electrical Engineering, Mechanical Engineering, or Reliability Engineering.
About the Company
Company: D Matrix
Headquarters: Santa Clara, CA, USA
d-Matrix develops software and hardware to enable generative AI, building next-generation AI compute platforms and scalable rack-level systems for data centers. The company focuses on hardware qualification, reliability, and high-performance AI infrastructure with a collaborative, inclusive culture.
