Senior Staff FPGA Engineer

Job Title

Senior Staff FPGA Engineer

Role Summary

Design and deliver high-performance FPGA prototypes for PCIe-based systems, from architecture through hardware bring-up and compliance testing. Work on a cross-functional engineering team in Porto to enable early validation of hardware and software prior to silicon availability.

Experience Level

Senior-level. Ideally 8+ years of FPGA design and development experience, with a track record of shipping production designs.

Responsibilities

Primary responsibilities include FPGA architecture, implementation, verification, and hardware validation for high-speed PCIe prototypes.

• Prototype and optimize PCIe-based designs on FPGA platforms using Vivado or similar toolchains (synthesis, place-and-route, timing closure, hardware bring-up).
• Simulate and verify prototype designs using industry-standard methodologies (for example UVM) prior to FPGA implementation.
• Perform timing analysis and optimization across multiple clock domains; resolve setup and hold violations.
• Collaborate with hardware, software, and verification teams to define requirements, evaluate tradeoffs, and deliver integrated FPGA solutions.
• Develop and execute test plans to validate functionality, performance, and reliability of FPGA prototypes in real-world conditions.
• Participate in PCI-SIG compliance workshops and perform official compliance testing of PCIe prototypes.
• Debug and resolve hardware, protocol, and system-level issues discovered during compliance testing and bring-up.

Requirements

Must-have technical skills and practical experience; plus a couple of desirable skills.

• Must-have: Extensive hands-on FPGA design experience and history of delivering working designs in production or prototype environments.
• Must-have: Deep proficiency in Verilog and RTL design (complex state machines, pipelines, multi-clock-domain architectures).
• Must-have: Strong command of Vivado or similar FPGA toolchains including synthesis, implementation, and timing-closure workflows.
• Must-have: Solid understanding of digital design fundamentals: clock-domain crossings, metastability, timing constraints, and static timing analysis.
• Must-have: Experience with high-speed interfaces such as PCIe or Ethernet, including protocol-level debugging.
• Must-have: Experience with simulation and verification practices appropriate for FPGA prototypes (for example UVM).
• Nice-to-have: Scripting experience (Python or Tcl) for automation and tooling.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field; or equivalent practical/hands-on experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.