Senior Staff Formal Verification Engineer

Job Title

Senior Staff Formal Verification Engineer

Role Summary

As a Senior Staff Formal Verification Engineer in the Solutions Group at the Bangalore Design Center, you will design and maintain end-to-end formal verification flows, develop assertions and proofs for complex RTL, and work with RTL designers to eliminate corner-case bugs before silicon.

You will be responsible for integrating formal methods into the verification process, mentoring engineers, and building reusable verification infrastructure.

Experience Level

Senior-level — typically 8+ years in digital design or verification, with at least 5 years focused on formal verification techniques.

Responsibilities

Primary responsibilities include:

• Build and maintain end-to-end formal verification flows integrated with the broader verification process.
• Create formal verification plans; develop assertions, assumptions, and cover properties that target key behaviors.
• Apply formal techniques such as bounded model checking, induction, and abstraction to prove RTL correctness.
• Set up and run proofs using formal tools; develop proof strategies and debug failed proofs.
• Trace counterexamples back to RTL or verification-environment root causes and drive fixes.
• Maintain and extend assertion libraries usable in both simulation and formal contexts.
• Guide, train, and mentor design and verification engineers on effective use of formal methods.

Requirements

Must-have skills and experience:

• 8+ years industry experience in digital design or verification; 5+ years focused on formal verification.
• Deep understanding of digital logic, RTL design patterns, and synthesis/timing flows.
• Hands-on proficiency with Verilog or SystemVerilog and debugging complex RTL.
• Strong grasp of temporal logic and assertion-based verification (SVA or PSL).
• Practical experience with formal tools (e.g., Jasper, VC-Formal) including setup, proof strategies, and debug.
• Proven track record of using formal methods to close verification on complex projects.

Nice-to-have:

• Experience with Python, Perl, or shell scripting.
• Prior mentoring or leadership experience on verification teams.

Education Requirements

Bachelor's or Master's degree in Computer Science or Electrical Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.