Senior Staff Engineer, Static Timing Analysis (STA) Lead

Job Title

Senior Staff Engineer, Static Timing Analysis (STA) Lead

Role Summary

Lead technical owner for static timing analysis (STA) on next-generation, high-speed data-center CPU designs. Drive timing sign-off criteria, advanced timing methodologies, and platform-level tracking to accelerate timing closure across complex SoC/CPU blocks.

Experience Level

Senior — senior-level engineering role. The posting specifies 10+ years of relevant experience.

Responsibilities

Provide technical leadership for timing across the CPU design flow and establish methods and tools to ensure timely sign-off.

• Serve as primary STA subject-matter expert and point of contact for high-speed CPU teams.
• Define timing sign-off criteria, margins, and closure strategies for complex blocks.
• Develop and deploy correct-by-construction timing methodologies early in the design cycle.
• Architect and maintain timing-tracking platforms and metrics for convergence analysis.
• Lead SDC quality assurance and constraint management across flows.
• Collaborate with synthesis, place & route, and verification teams to resolve timing issues.

Requirements

Must-have technical skills and domain experience.

• Deep, authoritative understanding of the full timing sign-off process and closure techniques.
• Expert-level experience with Synopsys PrimeTime.
• Hands-on experience taping out complex designs at 3nm (N3) process node.
• Strong working knowledge of the physical design flow from synthesis through place and route.
• Extensive experience developing, managing, and debugging complex SDCs for large SoC/CPU designs.
• Strong understanding of advanced clocking and CTS architectures, including Mesh and MSCTS.
• Proven ability to lead cross-functional timing closure efforts and improve team methodologies.
• Excellent communication and mentorship skills for guiding engineers on timing practices.
• Nice-to-have: experience with Synopsys FusionCompiler, 2nm (N2) exposure, ML-based timing prediction methods, and prior work on data-center scale CPU timing closure.

Education Requirements

Required: Bachelor's or Master's degree (or PhD) in Electrical & Electronics, Electrical & Computer Engineering, Computer Science, VLSI, or closely related field. The posting specifies this education requirement alongside 10+ years of relevant industry experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.