Senior Staff Engineer, Physical Verification
RenesasJob Title
Senior Staff Engineer, Physical Verification
Role Summary
Lead signoff physical verification and tapeout readiness for advanced ASIC/SoC block and full-chip layouts. Collaborate with Physical Design, Layout, Foundry/PDK, and program teams to ensure manufacturing requirements are met before tapeout.
Experience Level
Senior - typically 10–15 years of experience in Physical Verification, Physical Design, or backend implementation.
Responsibilities
Execute signoff verification, drive closure of violations, maintain foundry-qualified flows, and produce final signoff evidence for tapeout.
- Perform and drive signoff PV for block- and chip-level designs.
- Run and analyze DRC, LVS, ERC, Antenna, and Density checks using signoff tools.
- Debug verification violations and provide actionable recommendations to Physical Design and Layout teams.
- Track, prioritize, and drive closure of signoff issues through cross-functional collaboration.
- Maintain and support foundry-qualified rule decks, runsets, and waiver management processes.
- Coordinate verification re-runs after design changes/ECOs to detect regressions and maintain signoff quality.
- Generate signoff status reports, metrics, and violation summaries for project reviews.
- Prepare final signoff evidence including clean DRC/LVS reports, waiver summaries, and residual risk assessments for tapeout reviews.
Requirements
Must-have skills and practical experience required for successful performance in the role.
- 10–15 years' experience in Physical Verification, Physical Design, or backend implementation.
- Expertise in DRC, LVS, ERC, Antenna, and Density verification methodologies.
- Hands-on experience with Calibre, Pegasus, or equivalent physical verification tools.
- Strong understanding of foundry signoff requirements and PDKs; experience managing rule decks and waivers.
- Proven ability to debug and resolve complex signoff violations at block and full-chip levels.
- Familiarity with GDSII/OASIS databases, netlists, and tapeout processes.
- Proficiency in scripting (Tcl, Python, Perl, or Shell).
- Preferred: experience with advanced nodes (7nm, 5nm, 3nm), knowledge of Physical Design/PDN/STA flows, and multiple SoC tapeouts.
Education Requirements
Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
