Senior Staff Engineer - Memory IP Applications Engineering

Job Title

Senior Staff Engineer - Memory IP Applications Engineering

Role Summary

Provide technical leadership and customer-facing support for integration, validation, and silicon bring-up of Memory Subsystem and Interface IP in ASIC/SoC designs. Work as part of a multi-site applications engineering team to enable successful deployment of Synopsys memory IP in customer products.

Focus areas include integration reviews, system bring-up, troubleshooting across the design flow, and transferring best practices to customers and internal teams.

Experience Level

Senior-level - typically 10+ years of industry experience (the posting specifies a Master's with 10+ years or equivalent).

Responsibilities

The role combines customer engagement, hands-on integration support, and cross-functional product feedback.

• Provide technical guidance and hands-on support for customers integrating Memory Subsystem IP into ASIC/SoC designs.
• Conduct detailed integration reviews at key customer milestones and troubleshoot complex issues across simulation, synthesis, floorplanning, and timing closure.
• Collaborate with customers and internal teams on RTL simulation, gate-level debugging, synthesis (Design Compiler/Fusion Compiler), and timing analysis (PrimeTime).
• Support silicon bring-up and system-level characterization in lab and system environments.
• Document best practices, develop application notes, and deliver training to enable customer success.
• Relay customer feedback to product teams to influence IP improvements and keep current with interface protocols and standards.
• Occasional travel to customer sites for on-site support, integration reviews, and system bring-up.

Requirements

Must-have technical skills and domain experience. See Education Requirements for degree expectations.

• 10+ years experience in IP design, ASIC/SoC integration, or customer-facing engineering roles (exceptional candidates considered).
• Solid understanding of ASIC design flows: simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.
• Hands-on expertise integrating and validating high-speed memory IP and memory subsystem components.
• Proficient in RTL and gate-level simulation debugging; familiarity with Design Compiler, Fusion Compiler, and PrimeTime.
• Experience with silicon bring-up and system-level characterization in lab environments.
• Strong communication, organization, customer-focus, and ability to manage multiple priorities under tight schedules.

Education Requirements

Preferred: Master’s degree (MSc/MS). The posting specifies "Masters with 10+ yrs of industry experience or equivalent." Fields implied include Electrical Engineering, Computer Engineering, Computer Science, or related technical disciplines. Equivalent practical experience or exceptional academic backgrounds with strong silicon debug experience are acceptable.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.