Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)

Job Title

Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)

Role Summary

Lead low-power (power intent) and formal equivalence verification activities for complex ASIC/SoC programs. Define and sign off UPF/CPF power intent, ensure correct low-power implementation across RTL-to-tapeout flows, and drive formal equivalence verification from RTL through synthesis, DFT, implementation, and ECOs.

Collaborate with Architecture, RTL, Verification, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness, low-power integrity, and tapeout readiness.

Experience Level

Senior-level - 10–15 years of experience in ASIC/SoC implementation, low-power design, or formal verification.

Responsibilities

Primary responsibilities include ownership of power intent and formal equivalence verification, debugging and closure of issues, and developing automation and reusable methodologies.

• Define, develop, and maintain power intent (UPF/CPF) and low-power architecture.
• Own power-domain and power-state specifications at IP, subsystem, and chip level.
• Drive implementation and integration of isolation, retention, level shifters, and power-switch methodologies.
• Debug and resolve power-intent issues across RTL, synthesis, implementation, and ECO stages.
• Execute formal equivalence checks at RTL ↔ Synthesis, Synthesis ↔ DFT, DFT ↔ Physical Design, and Pre-ECO ↔ Post-ECO milestones.
• Analyze and debug equivalence failures related to constraints, mapping, low-power insertion, DFT logic, and ECOs.
• Validate RTL, netlists, library models, constraints, and ECO patches; produce signoff-quality reports and support milestone/tapeout reviews.
• Develop automation, scripts, and reusable checks for low-power validation, equivalence verification, and issue tracking.
• Drive low-power and equivalence issue ownership, closure tracking, and tapeout readiness.

Requirements

Must-have skills and preferred qualifications relevant to the role.

• Must-have: 10–15 years of experience in ASIC/SoC implementation, low-power design, or formal verification.
• Must-have: Strong expertise with UPF/CPF-based low-power methodologies; practical knowledge of power domains, power states, isolation, retention, level shifters, and power gating.
• Must-have: Hands-on experience with Formal Equivalence Verification (FEV/LEC) tools and methodologies; strong understanding of synthesis, DFT, STA, ECO, and implementation flows.
• Must-have: Proficiency in scripting (Tcl, Python, Perl, or Shell) and strong debugging, analytical, and problem-solving skills.
• Nice-to-have: Experience with advanced-node technologies (7nm and below), physical design, PDN, STA, and signoff methodologies.
• Nice-to-have: Experience supporting full-chip SoC tapeouts and working across global design teams.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.