Senior Staff Engineer, Logic Design Verification
SynopsysJob Title
Senior Staff Engineer, Logic Design Verification
Role Summary
Lead verification of interface IP used in production silicon by architecting and implementing UVM-based testbenches, driving coverage closure, and mentoring verification engineers. The role focuses on functional and formal verification to ensure designs meet tape-out schedules and quality targets.
Experience Level
Senior - typically requires 8+ years of hands-on ASIC design verification experience with significant UVM and SystemVerilog expertise.
Responsibilities
Primary responsibilities include building verification environments, defining test plans, and improving team capability.
- Collaborate with design teams to define verification requirements and translate specifications into test plans covering functional, edge-case, and performance scenarios.
- Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components for interface IP.
- Develop SystemVerilog test sequences and constrained-random stimulus to stress designs and uncover corner cases before silicon.
- Implement SystemVerilog Assertions for simulation-based functional verification and formal flows.
- Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure.
- Lead and mentor verification engineers on UVM methodology, debugging techniques, testbench architecture, and best practices.
Requirements
Must-have technical skills and experience; nice-to-have items noted separately.
- Must-have: 8+ years of ASIC design verification experience with a strong focus on UVM-based functional verification.
- Must-have: Deep expertise in SystemVerilog, including advanced testbench architecture, constrained-random verification, and coverage-driven verification.
- Must-have: Proven experience implementing SystemVerilog Assertions for functional and formal verification flows.
- Must-have: Strong programming skills in at least two of: C, SystemVerilog, TCL, Perl, Python.
- Nice-to-have: Experience with PCI Express and CXL protocols.
- Nice-to-have: Experience with formal verification tools such as Jasper or VC Formal.
- Nice-to-have: Familiarity with AI-assisted coding tools (e.g., Cursor, GitHub Copilot) and verification IP reuse patterns.
Education Requirements
Bachelor's or master’s degree in Computer Engineering, Electrical Engineering, or Communication Engineering.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
