Senior Staff Engineer, Layout Design (Power & Analog ICs)
RenesasJob Title
Senior Staff Engineer, Layout Design (Power & Analog ICs)
Role Summary
Senior individual-contributor responsible for layout architecture and execution of analog, power, and mixed-signal IC blocks through full-chip integration and tape-out readiness. Works closely with circuit designers, CAD, process, package, reliability, and verification teams.
Primary focus areas include PMICs, linear and switching regulators, gate drivers, battery-management ICs, and other power/analog devices. Expected to improve methodology and automation, own complex layout problems, and mentor engineers.
Experience Level
Senior - typically 10+ years of relevant experience in analog, power, or mixed-signal IC layout and associated flows (block-level and chip-level integration).
Responsibilities
Accountable for layout planning, execution, verification, and mentoring to deliver manufacturable, reliable analog and power ICs.
- Own floor planning and physical implementation for complex analog, power, and mixed-signal blocks; contribute to full-chip floor planning.
- Translate circuit requirements into layouts that meet matching, isolation, current-density, thermal, reliability, and area constraints.
- Apply advanced layout techniques for device matching, parasitic reduction, noise isolation, high-current routing, electromigration robustness, IR-drop, and yield optimization.
- Drive routing, integration, and sign-off readiness for block- and chip-level layouts; ensure tape-out quality of layout databases and release documentation.
- Own and review physical verification activities (DRC, LVS, ERC, PEX, antenna, density, latch-up, reliability checks) and support post-layout simulation closure using extracted parasitics.
- Develop and deploy automation and reusable templates using SKILL, TCL, Python, Perl, or similar; improve layout methodology and IP portability across processes.
- Lead layout reviews, provide estimates, progress reports, risk assessments and recovery plans; mentor junior and mid-level engineers.
- Identify physical-design risks early and coordinate corrective actions with design, CAD, PDK, process, and package teams.
Requirements
Must-have technical skills, tools, and behaviors required to perform the role.
- Extensive hands-on experience with Cadence Virtuoso and physical verification tools such as Calibre, PVS, or equivalents; familiarity with extraction and reliability tools.
- Deep practical knowledge of matching, parasitic control, guard rings, latch-up prevention, high-current routing, electromigration, IR-drop, and thermal effects in layout.
- Proven track record owning complex block-level layouts and contributing to full-chip integration and tape-out.
- Experience with deep-submicron CMOS processes; experience with BCD or high-voltage processes is preferred.
- Ability to automate layout/verification tasks using SKILL, TCL, Python, Perl, or similar scripting languages.
- Strong cross-functional communication skills, ability to operate independently on ambiguous problems, and experience mentoring or leading technical reviews.
Nice-to-have:
- Specific experience with PMICs, battery-management ICs, gate drivers, or high-current power devices.
- Experience improving PDKs, flow issues, tool evaluation, or driving CAD/process improvements across sites.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline (as stated in the posting).
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
