Senior Staff Engineer - Layout Design

Job Title

Senior Staff Engineer - Layout Design

Role Summary

Lead physical layout design for high-speed analog and mixed-signal IP blocks (SerDes, PLLs, TX/RX, and custom digital paths). Work within the Analog and Mixed Signal IP group to deliver tapeout-ready layouts and support top-level SoC integration.

Experience Level

Senior — typically requires 6+ years of relevant, hands-on experience in analog and mixed-signal custom IC layout, especially for high-speed circuits and advanced process nodes.

Responsibilities

You will be responsible for producing production-quality layouts and improving team throughput through automation and verification rigor.

• Design and own physical layout for SerDes, PLLs, RX/TX circuits, and custom digital blocks.
• Execute full layout verification flows (DRC, LVS, parasitic extraction) to ensure tapeout readiness.
• Collaborate with circuit designers to translate schematics into optimized layouts that meet performance, area, and reliability targets.
• Apply advanced floorplanning to address signal integrity, EM/IR, power distribution, and ESD/latchup constraints in FinFET and deep-submicron processes.
• Generate LEFs and support top-level integration for SoC assembly.
• Debug layout issues using parasitic extraction and simulation correlation across the verification stack.
• Develop and maintain scripts to automate layout tasks and improve consistency and turnaround time.

Requirements

Must-have technical skills and experience.

• 6+ years of hands-on experience in analog and mixed-signal custom IC layout, with exposure to high-speed analog circuits.
• Proven experience with Cadence Virtuoso / Custom Designer for layout implementation.
• Strong working knowledge of Calibre, ICV, and STAR-RXCT for DRC, LVS, and parasitic extraction.
• Solid understanding of CMOS and FinFET layout techniques, deep-submicron effects, and mitigation strategies.
• Experience with LEF generation, top-level integration, EM/IR analysis, and DFM considerations.
• Familiarity with ESD and latchup layout techniques is a plus.
• Ability to work independently, own blocks through integration, and clearly communicate layout tradeoffs to circuit designers.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering. (No certifications specified.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.