Senior Staff Engineer, Layout Design

Job Title

Senior Staff Engineer, Layout Design

Role Summary

Lead layout development for DDR and HBM PHY IP across advanced process nodes (7nm, 5nm, 3nm), focusing on floorplanning, layout closure, and manufacturability for analog and mixed-signal blocks. Work within the Silicon IP team to deliver memory-interface PHYs used in data center, AI, and mobile systems.

Experience Level

Senior - typically requires 8+ years of hands-on layout design experience in deep-submicron CMOS technologies.

Responsibilities

Primary responsibilities include technical leadership, project execution, and mentorship while remaining hands-on for critical layout tasks.

• Lead layout development for next-generation DDR and HBM PHY IP across FinFET and GAA nodes.
• Drive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks.
• Estimate effort, plan schedules, and coordinate execution across design, verification, and customer teams.
• Conduct and lead layout reviews; manage quality checks using Calibre and internal flows; generate LEF and IO frame designs.
• Translate PHY-level customer requirements into actionable layout constraints and resolve pitch, area, and integration challenges.
• Mentor junior layout engineers and elevate senior engineers' delivery quality.
• Remain hands-on to unblock critical technical issues during tight schedules.

Requirements

Must-have technical skills and experience; nice-to-have items noted.

• 8+ years of hands-on layout experience in deep-submicron CMOS technologies, with direct exposure to 7nm or below.
• Demonstrated ability to lead layout projects from floorplan through tapeout, including estimation and resource planning.
• Deep expertise in layout matching techniques, ESD design, latch-up prevention, PERC/EMIR analysis, DFM rules, LEF generation, and IO frame layout.
• Strong understanding of FinFET and GAA process effects, including fin quantization and advanced-node routing constraints.
• Proficiency with Cadence Virtuoso, Calibre, and other industry-standard layout and verification tools.
• Effective technical communication and cross-functional collaboration skills.
• Nice-to-have: direct experience with memory PHY IP (DDR, HBM, LPDDR) and customer-facing integration work.

Education Requirements

Bachelor's or Master’s degree in Electronics Engineering, Electrical Engineering, or a related field (as stated in the source).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.