Senior Staff Engineer, Front-End Verification

Job Title

Senior Staff Engineer, Front-End Verification

Role Summary

Individual contributor on the front-end design verification (DV) team responsible for unit-level verification of CPU front-end blocks: instruction fetch, branch prediction, and related fetch control structures.

The role focuses on building and maintaining UVM testbenches, generating stimulus, developing checkers and C++ reference models, and collaborating with RTL and other teams to close complex microarchitectural bugs.

Experience Level

Senior level. The posting identifies this as a Sr./Staff role; no specific years-of-experience were stated.

Responsibilities

Primary responsibilities for this role include:

• Design, build, and maintain unit-level UVM testbenches for instruction fetch, branch predictors, and related sub-blocks.
• Create constrained-random and directed stimulus targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
• Develop checkers, scoreboards, and transactors for accurate cycle- or transaction-level verification.
• Integrate and maintain C++ reference models and predictors used for verification checking.
• Execute verification plans, track functional and code coverage, and drive closure on edge cases and regressions.
• Work closely with RTL designers, performance modeling, and software teams to trace and fix misspeculation and redirect issues.

Requirements

Must-have skills and experience; a short list of desirable additions is noted separately.

• Must-have: Proven experience verifying CPU front-end blocks (instruction fetch, branch predictors such as BTB/TAGE/RAS, instruction caches/TLBs, or decode) at unit level.
• Must-have: Strong SystemVerilog and UVM expertise for writing controllable unit testbench environments.
• Must-have: Experience integrating C++ reference models or checkers into verification frameworks.
• Must-have: Skill developing constrained-random and directed tests and building reusable transactors, scoreboards, and checkers.
• Must-have: Hands-on debugging of microarchitectural fetch, misprediction, and redirect issues in collaboration with RTL teams.
• Nice-to-have: Experience with Verilator, emulation flows, or other open-source/industry simulators; prior exposure to RISC-V front-end microarchitecture.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.