Senior Staff Engineer - Front-End ASIC Digital Design
SynopsysJob Title
Senior Staff Engineer - Front-End ASIC Digital Design
Role Summary
Design and deliver synthesizable RTL for high-performance SoC blocks, drive front-end sign-off (STA, lint, CDC/RDC, synthesis, power), and hand off clean designs to physical implementation. Work within an ASIC Digital Design team collaborating with analog, physical design, and applications engineering.
Experience Level
Senior - requires 8+ years of ASIC design experience with front-end sign-off and timing-closure responsibility.
Responsibilities
Primary responsibilities include front-end development, verification, and sign-off.
- Translate architecture and micro-architecture into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems.
- Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.
- Develop and review SDC constraints; support full-chip timing closure and static timing analysis (STA).
- Execute lint and CDC/RDC checks and ensure designs meet sign-off criteria before hand-off to physical design.
- Apply formal property verification (VC Formal) and assertion-based verification (SVA) at block level.
- Run power estimation and analysis and feed findings back into RTL optimization.
- Contribute to methodology improvements, scripting, and regression automation.
Requirements
Must-have technical skills and experience.
- Practical experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.
- Proficiency in SystemVerilog/Verilog RTL coding for synthesis.
- Familiarity with synthesis tools (Design Compiler / Fusion Compiler) and QoR analysis.
- Experience with low-power RTL techniques: clock gating, power gating, multi-Vt, and UPF.
- SDC constraint development and timing-closure methodology.
- Scripting and automation skills: TCL, Python, Perl; comfortable in Linux/UNIX environments.
- Strong digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB).
- High-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI).
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (BS/MS in EE/CE or similar) as stated in the posting.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
