Senior Staff Engineer, Digital IC Design

Job Title

Senior Staff Engineer, Digital IC Design

Role Summary

Senior engineer on the Custom Compute, Storage and Automotive Business Unit responsible for digital SoC integration, RTL design leadership, and driving designs to tape-out. Work spans architecture, implementation, verification, and post-silicon debug with cross-disciplinary teams.

Experience Level

Senior. See Education Requirements for years-of-experience guidance.

Responsibilities

Accountable for a portion of SoC design and integration through tape-out and post-silicon validation.

• Integrate internal and external IP blocks at the chip level and collaborate with the SOC Integration team.
• Own portions of SoC design from specification through completion, including floorplanning and IP interconnect.
• Perform static checks and support subsystem and chip-level verification and gate-level simulations.
• Drive timing closure; define and manage timing constraints, clock/reset architecture, and CDC strategies.
• Lead RTL design efforts for processor IP to meet architectural requirements and deliver micro-architectural specifications.
• Work closely with verification and implementation teams to satisfy product requirements and resolve issues through post-silicon debug.
• Use industry and internal EDA tools for functional and gate-level simulation and code quality checks.
• Participate in automation tool development and apply next-generation AI tools to improve workflows.

Requirements

Core technical skills and hands-on experience required; listed as must-haves and a few nice-to-haves.

• Must-have: Proven experience taping out complex SoCs and performing post-silicon debug.
• Must-have: Strong RTL design skills in SystemVerilog and knowledge of front-end RTL decisions and their impact on physical implementation and verification.
• Must-have: Hands-on SoC integration experience including clock/reset design, CDC, and managing timing constraints.
• Must-have: Familiarity with ARM protocols (APB, AHB, AXI, CHI) and SoC interconnect architectures.
• Must-have: Experience with functional and gate-level simulation flows and using industry EDA tools.
• Must-have: Proficiency with scripting languages such as Python or Tcl.
• Must-have: Strong communication, problem-solving, and analytical skills.
• Nice-to-have: Experience leading design of internally developed processor IP and contributing to automation tools or AI-driven workflows.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 5+ years of relevant experience; or a Master's/PhD with 3+ years of relevant experience. Equivalent practical experience is acceptable.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.