Senior Staff Engineer, Digital IC Design

Job Title

Senior Staff Engineer Design

Role Summary

Lead micro-architecture and RTL development for SoC IP with emphasis on high-density, performance SRAM compilers and associated interfaces. Work on HW/SW co-design across multifunction teams within Central Engineering to deliver timing- and performance-critical silicon IP.

This is a hands-on engineering role that coordinates with architects, verification, and integration teams to produce production-quality silicon building blocks used across Marvell products.

Experience Level

Senior-level. The posting indicates typical experience profiles of approximately 8–12 years with a bachelor’s degree or 5–7 years with a master’s/PhD; expect 8+ years of relevant industry experience for this role.

Responsibilities

Primary responsibilities include leading design and delivery of SoC component IP and collaborating across teams to meet performance, timing, and power targets.

• Lead micro-architecture and RTL design for SoC and component IP (memory controllers, PCIe/CXL, etc.).
• Drive HW/SW co-design and integration with system architects and verification teams.
• Develop and optimize timing-critical designs, including timing closure and power optimization.
• Ensure RTL quality through lint, CDC reviews, and static checks.
• Deliver production-quality designs on aggressive schedules and support SoC integration.

Requirements

Must-have technical skills, plus a few preferred areas of domain expertise.

• Strong, hands-on understanding of SoC architecture, processor cores, memory subsystems, and peripheral interfaces.
• Extensive experience with Verilog or VHDL and RTL quality tools (lint, CDC, Spyglass).
• Proficient in scripting for design automation and tooling (Perl, Python, or similar).
• Proven record of delivering production-quality silicon IP under tight schedules; experience with SOC integration.
• Knowledge of timing closure and power optimization methodologies.
• May require eligibility for access to export-controlled technology; candidates might be subject to export license review.
• Nice-to-have: Domain expertise in CXL/PCIe protocols and DDR memory controllers.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field is stated. A Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields is listed as an alternative with reduced years-of-experience. The posting ties degree level to experience expectations (e.g., B.S. + ~8–12 years; M.S./PhD + ~5–7 years).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.